Lines Matching +full:mdio +full:- +full:gpio
1 Common MDIO bus multiplexer/switch properties.
3 An MDIO bus multiplexer/switch will have several child busses that are
4 numbered uniquely in a device dependent manner. The nodes for an MDIO
8 - #address-cells = <1>;
9 - #size-cells = <0>;
12 - mdio-parent-bus : phandle to the parent MDIO bus.
14 - Other properties specific to the multiplexer/switch hardware.
17 - #address-cells = <1>;
18 - #size-cells = <0>;
19 - reg : The sub-bus number.
24 /* The parent MDIO bus. */
25 smi1: mdio@1180000001900 {
26 compatible = "cavium,octeon-3860-mdio";
27 #address-cells = <1>;
28 #size-cells = <0>;
33 An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
34 pair of GPIO lines. Child busses 2 and 3 populated with 4
37 mdio-mux {
38 compatible = "mdio-mux-gpio";
40 mdio-parent-bus = <&smi1>;
41 #address-cells = <1>;
42 #size-cells = <0>;
44 mdio@2 {
46 #address-cells = <1>;
47 #size-cells = <0>;
49 phy11: ethernet-phy@1 {
51 marvell,reg-init = <3 0x10 0 0x5777>,
55 interrupt-parent = <&gpio>;
58 phy12: ethernet-phy@2 {
60 marvell,reg-init = <3 0x10 0 0x5777>,
64 interrupt-parent = <&gpio>;
67 phy13: ethernet-phy@3 {
69 marvell,reg-init = <3 0x10 0 0x5777>,
73 interrupt-parent = <&gpio>;
76 phy14: ethernet-phy@4 {
78 marvell,reg-init = <3 0x10 0 0x5777>,
82 interrupt-parent = <&gpio>;
87 mdio@3 {
89 #address-cells = <1>;
90 #size-cells = <0>;
92 phy21: ethernet-phy@1 {
94 marvell,reg-init = <3 0x10 0 0x5777>,
98 interrupt-parent = <&gpio>;
101 phy22: ethernet-phy@2 {
103 marvell,reg-init = <3 0x10 0 0x5777>,
107 interrupt-parent = <&gpio>;
110 phy23: ethernet-phy@3 {
112 marvell,reg-init = <3 0x10 0 0x5777>,
116 interrupt-parent = <&gpio>;
119 phy24: ethernet-phy@4 {
121 marvell,reg-init = <3 0x10 0 0x5777>,
125 interrupt-parent = <&gpio>;