Lines Matching +full:port +full:- +full:1
6 - compatible: may be compatible = "mediatek,mt7530"
9 - #address-cells: Must be 1.
10 - #size-cells: Must be 0.
11 - mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12 on multi-chip module belong to MT7623A has or the remotely standalone
17 - core-supply: Phandle to the regulator node necessary for the core power.
18 - io-supply: Phandle to the regulator node necessary for the I/O power.
19 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
24 - reset-gpios: Should be a gpio specifier for a reset line.
28 - resets : Phandle pointing to the system reset controller with
30 - reset-names : Should be set to "mcm".
34 - reg: Port address described must be 6 for CPU port and from 0 to 5 for
36 - phy-mode: String, the following values are acceptable for port labeled
41 must be either "sgmii", "1000base-x" or "2500base-x"
43 Port 5 of mt7530 and mt7621 switch is muxed between:
44 1. GMAC5: GMAC5 can interface with another external MAC or PHY.
45 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
46 of the SOC. Used in many setups where port 0/4 becomes the WAN port.
48 GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
51 Port 5 modes/configurations:
52 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
54 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
56 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
57 It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
59 3. Port 5 is muxed to GMAC5 and can interface to an external phy.
60 Port 5 becomes an extra switch port.
61 Only works on platform where external phy TX<->RX lines are swapped.
62 Like in the Ubiquiti ER-X-SFP.
63 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
64 Currently a 2nd CPU port is not supported by DSA code.
67 1. normal: The PHY can only connect to 2nd GMAC but not to the switch
69 a ethernet port. But can't interface to the 2nd GMAC.
71 Based on the DT the port 5 mode is configured.
73 Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
74 When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
75 phy-mode must be set, see also example 2 below!
76 * mt7621: phy-mode = "rgmii-txid";
77 * mt7623: phy-mode = "rgmii";
81 - gpio-controller: Boolean; if defined, MT7530's LED controller will run on
83 - #gpio-cells: Must be 2 if gpio-controller is defined.
84 - interrupt-controller: Boolean; Enables the internal interrupt controller.
86 If interrupt-controller is defined, the following properties are required.
88 - #interrupt-cells: Must be 1.
89 - interrupts: Parent interrupt for the interrupt controller.
100 #address-cells = <1>;
101 #size-cells = <0>;
104 core-supply = <&mt6323_vpa_reg>;
105 io-supply = <&mt6323_vemc3v3_reg>;
106 reset-gpios = <&pio 33 0>;
109 #address-cells = <1>;
110 #size-cells = <0>;
112 port@0 {
117 port@1 {
118 reg = <1>;
122 port@2 {
127 port@3 {
132 port@4 {
137 port@6 {
141 phy-mode = "trgmii";
142 fixed-link {
144 full-duplex;
151 Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
155 compatible = "mediatek,eth-mac";
157 phy-mode = "rgmii";
159 fixed-link {
161 full-duplex;
166 gmac1: mac@1 {
167 compatible = "mediatek,eth-mac";
168 reg = <1>;
169 phy-mode = "rgmii-txid";
170 phy-handle = <&phy4>;
173 mdio: mdio-bus {
174 #address-cells = <1>;
175 #size-cells = <0>;
178 phy4: ethernet-phy@4 {
182 mt7530: switch@1f {
184 #address-cells = <1>;
185 #size-cells = <0>;
187 pinctrl-names = "default";
191 reset-names = "mcm";
194 #address-cells = <1>;
195 #size-cells = <0>;
197 port@0 {
202 port@1 {
203 reg = <1>;
207 port@2 {
212 port@3 {
217 /* Commented out. Port 4 is handled by 2nd GMAC.
218 port@4 {
224 cpu_port0: port@6 {
228 phy-mode = "rgmii";
230 fixed-link {
232 full-duplex;
241 Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
245 compatible = "mediatek,eth-mac";
247 phy-mode = "rgmii";
249 fixed-link {
251 full-duplex;
256 mdio: mdio-bus {
257 #address-cells = <1>;
258 #size-cells = <0>;
261 ephy5: ethernet-phy@7 {
265 mt7530: switch@1f {
267 #address-cells = <1>;
268 #size-cells = <0>;
270 pinctrl-names = "default";
274 reset-names = "mcm";
277 #address-cells = <1>;
278 #size-cells = <0>;
280 port@0 {
285 port@1 {
286 reg = <1>;
290 port@2 {
295 port@3 {
300 port@4 {
305 port@5 {
308 phy-mode = "rgmii";
309 phy-handle = <&ephy5>;
312 cpu_port0: port@6 {
316 phy-mode = "rgmii";
318 fixed-link {
320 full-duplex;