Lines Matching full:flash
4 flash chips. It has a memory-mapped register interface for both control
6 paired with a custom DMA engine (inventively named "Flash DMA") which supports
36 (optional) Flash DMA register range (if present)
37 (optional) NAND flash cache range (if at non-standard offset)
40 "flash-dma" or "flash-edu" and/or "nand-cache".
41 - interrupts : The NAND CTLRDY interrupt, (if Flash DMA is available)
98 to represent enabled chip-selects which (may) contain NAND flash chips. Their
111 - nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
117 out the parity bytes it stores on the flash.
119 the flash geometry (particularly the NAND page
125 Each nandcs device node may optionally contain sub-nodes describing the flash
135 reg-names = "nand", "flash-dma";
145 nand-on-flash-bbt;
182 nand-on-flash-bbt;