Lines Matching +full:read +full:- +full:delay

1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 	"sdio" - SDIO source clock (required)
16 	"enable" - gate clock which used for enabling/disabling the device (required)
17 	"2x_enable" - gate clock controlling the device for some special platforms (optional)
20 - assigned-clocks: the same with "sdio" clock
21 - assigned-clock-parents: the default parent of "sdio" clock
22 - pinctrl-names: should be "default", "state_uhs"
23 - pinctrl-0: should contain default/high speed pin control
24 - pinctrl-1: should contain uhs mode pin control
26 PHY DLL delays are used to delay the data valid window, and align the window
29 write line delay value, clock read command line delay value, clock read data
30 positive edge delay value and clock read data negative edge delay value.
31 Each cell's delay value unit is cycle of the PHY clock.
33 - sprd,phy-delay-legacy: Delay value for legacy timing.
34 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
37 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
39 - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
46 	compatible  = "sprd,sdhci-r11";
50 	clock-names = "sdio", "enable";
53 	assigned-clocks = <&ap_clk CLK_EMMC_2X>;
54 	assigned-clock-parents = <&rpll CLK_RPLL_390M>;
56 	pinctrl-names = "default", "state_uhs";
57 	pinctrl-0 = <&sd0_pins_default>;
58 	pinctrl-1 = <&sd0_pins_uhs>;
60 	sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
61 	bus-width = <8>;
62 	non-removable;
63 	no-sdio;
64 	no-sd;
65 	cap-mmc-hw-reset;