Lines Matching +full:neg +full:- +full:edge

11 - compatible             : contains "arm,pl18x", "arm,primecell".
12 - vmmc-supply            : phandle to the regulator device tree node, mentioned
16 - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides
18 - resets                 : phandle to internal reset line.
20 - vqmmc-supply           : phandle to the regulator device tree node, mentioned
23 - st,sig-dir-dat0        : bus signal direction pin used for DAT[0].
24 - st,sig-dir-dat2        : bus signal direction pin used for DAT[2].
25 - st,sig-dir-dat31       : bus signal direction pin used for DAT[3] and DAT[1].
26 - st,sig-dir-dat74       : bus signal direction pin used for DAT[4] to DAT[7].
27 - st,sig-dir-cmd         : cmd signal direction pin used for CMD.
28 - st,sig-pin-fbclk       : feedback clock signal pin used.
31 - reg			 : a second base register may be defined if a delay
33 - st,sig-dir             : signal direction polarity used for cmd, dat0 dat123.
34 - st,neg-edge            : data & command phase relation, generated on
35                            sd clock falling edge.
36 - st,use-ckin            : use ckin pin from an external driver to sample
41 - mmc-cap-mmc-highspeed  : indicates whether MMC is high speed capable.
42 - mmc-cap-sd-highspeed   : indicates whether SD is high speed capable.
51 	dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
52 	       <&dma 29 0 0x0>; /* Logical - MemToDev */
53 	dma-names = "rx", "tx";
56 	clock-names = "sdi", "apb_pclk";
58 	max-frequency = <100000000>;
59 	bus-width = <4>;
60 	cap-sd-highspeed;
61 	cap-mmc-highspeed;
62 	cd-gpios  = <&gpio2 31 0x4>; // 95
63 	st,sig-dir-dat0;
64 	st,sig-dir-dat2;
65 	st,sig-dir-cmd;
66 	st,sig-pin-fbclk;
68 	vmmc-supply = <&ab8500_ldo_aux3_reg>;
69 	vqmmc-supply = <&vmmci>;
71 	pinctrl-names = "default", "sleep";
72 	pinctrl-0 = <&sdi0_default_mode>;
73 	pinctrl-1 = <&sdi0_sleep_mode>;