Lines Matching +full:timing +full:- +full:667000000
1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
39 const: nvidia,tegra30-mc
47 clock-names:
49 - const: mc
54 "#reset-cells":
57 "#iommu-cells":
60 "#interconnect-cells":
64 "^emc-timings-[0-9]+$":
67 nvidia,ram-code:
70 Value of RAM_CODE this timing set is used for.
73 "^timing-[0-9]+$":
76 clock-frequency:
82 nvidia,emem-configuration:
83 $ref: /schemas/types.yaml#/definitions/uint32-array
88 - description: MC_EMEM_ARB_CFG
89 - description: MC_EMEM_ARB_OUTSTANDING_REQ
90 - description: MC_EMEM_ARB_TIMING_RCD
91 - description: MC_EMEM_ARB_TIMING_RP
92 - description: MC_EMEM_ARB_TIMING_RC
93 - description: MC_EMEM_ARB_TIMING_RAS
94 - description: MC_EMEM_ARB_TIMING_FAW
95 - description: MC_EMEM_ARB_TIMING_RRD
96 - description: MC_EMEM_ARB_TIMING_RAP2PRE
97 - description: MC_EMEM_ARB_TIMING_WAP2PRE
98 - description: MC_EMEM_ARB_TIMING_R2R
99 - description: MC_EMEM_ARB_TIMING_W2W
100 - description: MC_EMEM_ARB_TIMING_R2W
101 - description: MC_EMEM_ARB_TIMING_W2R
102 - description: MC_EMEM_ARB_DA_TURNS
103 - description: MC_EMEM_ARB_DA_COVERS
104 - description: MC_EMEM_ARB_MISC0
105 - description: MC_EMEM_ARB_RING1_THROTTLE
108 - clock-frequency
109 - nvidia,emem-configuration
114 - nvidia,ram-code
119 - compatible
120 - reg
121 - interrupts
122 - clocks
123 - clock-names
124 - "#reset-cells"
125 - "#iommu-cells"
126 - "#interconnect-cells"
131 - |
132 memory-controller@7000f000 {
133 compatible = "nvidia,tegra30-mc";
136 clock-names = "mc";
140 #iommu-cells = <1>;
141 #reset-cells = <1>;
142 #interconnect-cells = <1>;
144 emc-timings-1 {
145 nvidia,ram-code = <1>;
147 timing-667000000 {
148 clock-frequency = <667000000>;
150 nvidia,emem-configuration = <