Lines Matching +full:11 +full:a
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
17 - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
18 - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
19 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
22 for a variety of connection possibilities including swapping pin order within
24 pairs which map a chip-specific VP output register to a 4-bit pin group. If
58 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
76 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
77 * and Y[11:4] across 16bits in the same pixclk cycle.
80 /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
82 /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
84 /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
100 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
118 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
119 * and Y[11:4] across 16bits in the same pixclk cycle.
122 /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
124 /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
126 /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
142 16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
160 * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over
164 /* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
166 /* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */