Lines Matching +full:single +full:- +full:master
5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
14 single interrupt must be specified.
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
21 here, there must be a corresponding entry in clock-names
24 - clock-names : List of clock names corresponding to the clocks specified in
31 Each bus master connected to an IOMMU must reference the IOMMU in its device
34 - iommus: A reference to the IOMMU in multiple cells. The first cell is a
36 A single master device can be connected to more than one iommu
39 master is connected to.
41 Example: mdp iommu and its bus master
44 compatible = "qcom,apq8064-iommu";
45 #iommu-cells = <1>;
46 clock-names =