Lines Matching +full:device +full:- +full:tree

1 This document describes the generic device tree binding for IOMMUs and their
5 IOMMU device node:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
26 Device nodes compatible with this binding represent hardware with some of the
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
43 The meaning of the IOMMU specifier is defined by the device tree binding of
44 the specific IOMMU. Below are a few examples of typical use-cases:
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
50 be multi-master yet only expose a single master in a given configuration.
52 - #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
54 address cell corresponds to the master device's ID. In some cases more than
56 - #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
58 device's ID for example, while the second cell could contain the start of
59 the DMA window for the given device. The length of the DMA window is given
62 Note that these are merely examples and real-world use-cases may use different
70 Devices that access memory through an IOMMU are called masters. A device can
74 --------------------
75 - iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU
76 master interfaces of the device. One entry in the list describes one master
77 interface of the device.
79 When an "iommus" property is specified in a device tree node, the IOMMU will
80 be used for address translation. If a "dma-ranges" property exists in the
81 device's parent node it will be ignored. An exception to this rule is if the
82 referenced IOMMU is disabled, in which case the "dma-ranges" property of the
83 parent shall take effect. Note that merely disabling a device tree node does
86 disable the IOMMU's device tree node in the first place because it would
90 --------------------
91 - pasid-num-bits: Some masters support multiple address spaces for DMA, by
93 this is 0, which means that the device only has one address space.
95 - dma-can-stall: When present, the master can wait for a transaction to
102 having to either put back-pressure on the master, or abort new faulting
105 Firmware has to opt-in stalling, because most buses and masters don't
118 a "dma-ranges" property in a bus device node (such as PCI host bridges). This
120 are not explicitly listed in the device tree (e.g. PCI devices). However, the
121 requirements of that use-case haven't been fully determined yet. Implementing
129 Single-master IOMMU:
130 --------------------
133 #iommu-cells = <0>;
140 Multiple-master IOMMU with fixed associations:
141 ----------------------------------------------
143 /* multiple-master IOMMU */
153 #iommu-cells = <0>;
168 Multiple-master IOMMU:
169 ----------------------
173 #iommu-cells = <1>;
177 /* device has master ID 42 in the IOMMU */
182 /* device has master IDs 23 and 24 in the IOMMU */
186 Multiple-master IOMMU with configurable DMA window:
187 ---------------------------------------------------
199 #iommu-cells = <4>;