Lines Matching +full:sc8280xp +full:- +full:based
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
14 Power Domain Controller (PDC) that is on always-on domain. In addition to
17 well detect interrupts when the GIC is non-operational.
28 - enum:
29 - qcom,qcs615-pdc
30 - qcom,qcs8300-pdc
31 - qcom,qdu1000-pdc
32 - qcom,sa8255p-pdc
33 - qcom,sa8775p-pdc
34 - qcom,sar2130p-pdc
35 - qcom,sc7180-pdc
36 - qcom,sc7280-pdc
37 - qcom,sc8180x-pdc
38 - qcom,sc8280xp-pdc
39 - qcom,sdm670-pdc
40 - qcom,sdm845-pdc
41 - qcom,sdx55-pdc
42 - qcom,sdx65-pdc
43 - qcom,sdx75-pdc
44 - qcom,sm4450-pdc
45 - qcom,sm6350-pdc
46 - qcom,sm8150-pdc
47 - qcom,sm8250-pdc
48 - qcom,sm8350-pdc
49 - qcom,sm8450-pdc
50 - qcom,sm8550-pdc
51 - qcom,sm8650-pdc
52 - qcom,sm8750-pdc
53 - qcom,x1e80100-pdc
54 - const: qcom,pdc
59 - description: PDC base register region
60 - description: Edge or Level config register for SPI interrupts
62 '#interrupt-cells':
65 interrupt-controller: true
67 qcom,pdc-ranges:
68 $ref: /schemas/types.yaml#/definitions/uint32-matrix
73 - description: starting PDC port
74 - description: GIC hwirq number for the PDC port
75 - description: number of interrupts in sequence
82 - compatible
83 - reg
84 - '#interrupt-cells'
85 - interrupt-controller
86 - qcom,pdc-ranges
91 - |
92 #include <dt-bindings/interrupt-controller/irq.h>
94 pdc: interrupt-controller@b220000 {
95 compatible = "qcom,sdm845-pdc", "qcom,pdc";
97 qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
98 #interrupt-cells = <2>;
99 interrupt-parent = <&intc>;
100 interrupt-controller;
103 wake-device {
104 interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;