Lines Matching +full:shared +full:- +full:pin

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   The controller's registers are organized as sets of eight 32-bit
12   interrupt is shared for all of the banks handled by the controller.
15   - Doug Berger <opendmb@gmail.com>
16   - Florian Fainelli <f.fainelli@gmail.com>
21       - enum:
22           - brcm,bcm7445-gpio
23       - const: brcm,brcmstb-gpio
31   "#gpio-cells":
34       The first cell is the pin number (within the controller's
35       pin space), and the second is used for the following:
36       bit[0]: polarity (0 for active-high, 1 for active-low)
38   gpio-controller: true
40   brcm,gpio-bank-widths:
41     $ref: /schemas/types.yaml#/definitions/uint32-array
49       The interrupt shared by all GPIO lines for this controller.
51   "#interrupt-cells":
56       - bits[3:0] trigger type and level flags
57         1 = low-to-high edge triggered
58         2 = high-to-low edge triggered
59         4 = active high level-sensitive
60         8 = active low level-sensitive
63   interrupt-controller: true
65   wakeup-source:
71   - compatible
72   - reg
73   - gpio-controller
74   - "#gpio-cells"
75   - brcm,gpio-bank-widths
80   - |
82         #gpio-cells = <2>;
83         #interrupt-cells = <2>;
84         compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
85         gpio-controller;
86         interrupt-controller;
88         interrupt-parent = <&irq0_intc>;
90         brcm,gpio-bank-widths = <32 32 32 24>;
94         #gpio-cells = <2>;
95         #interrupt-cells = <2>;
96         compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
97         gpio-controller;
98         interrupt-controller;
100         interrupt-parent = <&irq0_aon_intc>;
102         wakeup-source;
103         brcm,gpio-bank-widths = <18 4>;