Lines Matching +full:shared +full:- +full:pin
3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
17 Should be <2>. The first cell is the pin number (within the controller's
18 pin space), and the second is used for the following:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
31 The interrupt shared by all GPIO lines for this controller.
33 - interrupts-extended:
36 'interrupt-parent'. Wakeup-capable GPIO controllers often route their
40 - #interrupt-cells:
43 - bits[3:0] trigger type and level flags
44 1 = low-to-high edge triggered
45 2 = high-to-low edge triggered
46 4 = active high level-sensitive
47 8 = active low level-sensitive
49 See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
51 - interrupt-controller:
54 - wakeup-source:
59 #gpio-cells = <2>;
60 #interrupt-cells = <2>;
61 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
62 gpio-controller;
63 interrupt-controller;
65 interrupt-parent = <&irq0_intc>;
67 brcm,gpio-bank-widths = <32 32 32 24>;
71 #gpio-cells = <2>;
72 #interrupt-cells = <2>;
73 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
74 gpio-controller;
75 interrupt-controller;
77 interrupt-parent = <&irq0_aon_intc>;
79 interrupts-extended = <&irq0_aon_intc 0x6>,
81 wakeup-source;
82 brcm,gpio-bank-widths = <18 4>;