Lines Matching +full:smmu +full:- +full:v2
1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
4 ---
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Rob Clark <robdclark@gmail.com>
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
23 - items:
24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
26 - const: qcom,adreno-gmu-wrapper
32 reg-names:
40 clock-names:
46 - description: GMU HFI interrupt
47 - description: GMU interrupt
49 interrupt-names:
51 - const: hfi
52 - const: gmu
54 power-domains:
56 - description: CX power domain
57 - description: GX power domain
59 power-domain-names:
61 - const: cx
62 - const: gx
69 description: Reference to the AOSS side-channel message RAM
71 operating-points-v2: true
73 opp-table:
77 - compatible
78 - reg
79 - reg-names
80 - power-domains
81 - power-domain-names
86 - if:
91 - qcom,adreno-gmu-618.0
92 - qcom,adreno-gmu-630.2
97 - description: Core GMU registers
98 - description: GMU PDC registers
99 - description: GMU PDC sequence registers
100 reg-names:
102 - const: gmu
103 - const: gmu_pdc
104 - const: gmu_pdc_seq
107 - description: GMU clock
108 - description: GPU CX clock
109 - description: GPU AXI clock
110 - description: GPU MEMNOC clock
111 clock-names:
113 - const: gmu
114 - const: cxo
115 - const: axi
116 - const: memnoc
118 - if:
123 - qcom,adreno-gmu-635.0
124 - qcom,adreno-gmu-660.1
129 - description: Core GMU registers
130 - description: Resource controller registers
131 - description: GMU PDC registers
132 reg-names:
134 - const: gmu
135 - const: rscc
136 - const: gmu_pdc
139 - description: GMU clock
140 - description: GPU CX clock
141 - description: GPU AXI clock
142 - description: GPU MEMNOC clock
143 - description: GPU AHB clock
144 - description: GPU HUB CX clock
145 - description: GPU SMMU vote clock
146 clock-names:
148 - const: gmu
149 - const: cxo
150 - const: axi
151 - const: memnoc
152 - const: ahb
153 - const: hub
154 - const: smmu_vote
156 - if:
161 - qcom,adreno-gmu-640.1
166 - description: Core GMU registers
167 - description: GMU PDC registers
168 - description: GMU PDC sequence registers
169 reg-names:
171 - const: gmu
172 - const: gmu_pdc
173 - const: gmu_pdc_seq
175 - if:
180 - qcom,adreno-gmu-650.2
185 - description: Core GMU registers
186 - description: Resource controller registers
187 - description: GMU PDC registers
188 - description: GMU PDC sequence registers
189 reg-names:
191 - const: gmu
192 - const: rscc
193 - const: gmu_pdc
194 - const: gmu_pdc_seq
196 - if:
201 - qcom,adreno-gmu-640.1
202 - qcom,adreno-gmu-650.2
207 - description: GPU AHB clock
208 - description: GMU clock
209 - description: GPU CX clock
210 - description: GPU AXI clock
211 - description: GPU MEMNOC clock
212 clock-names:
214 - const: ahb
215 - const: gmu
216 - const: cxo
217 - const: axi
218 - const: memnoc
220 - if:
225 - qcom,adreno-gmu-730.1
226 - qcom,adreno-gmu-740.1
231 - description: Core GMU registers
232 - description: Resource controller registers
233 - description: GMU PDC registers
234 reg-names:
236 - const: gmu
237 - const: rscc
238 - const: gmu_pdc
241 - description: GPU AHB clock
242 - description: GMU clock
243 - description: GPU CX clock
244 - description: GPU AXI clock
245 - description: GPU MEMNOC clock
246 - description: GMU HUB clock
247 - description: GPUSS DEMET clock
248 clock-names:
250 - const: ahb
251 - const: gmu
252 - const: cxo
253 - const: axi
254 - const: memnoc
255 - const: hub
256 - const: demet
259 - qcom,qmp
261 - if:
265 const: qcom,adreno-gmu-wrapper
270 - description: GMU wrapper register space
271 reg-names:
273 - const: gmu
276 - clocks
277 - clock-names
278 - interrupts
279 - interrupt-names
280 - iommus
281 - operating-points-v2
284 - |
285 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
286 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
287 #include <dt-bindings/interrupt-controller/irq.h>
288 #include <dt-bindings/interrupt-controller/arm-gic.h>
291 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
296 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
302 clock-names = "gmu", "cxo", "axi", "memnoc";
306 interrupt-names = "hfi", "gmu";
308 power-domains = <&gpucc GPU_CX_GDSC>,
310 power-domain-names = "cx", "gx";
313 operating-points-v2 = <&gmu_opp_table>;
317 compatible = "qcom,adreno-gmu-wrapper";
319 reg-names = "gmu";
320 power-domains = <&gpucc GPU_CX_GDSC>,
322 power-domain-names = "cx", "gx";