Lines Matching +full:panel +full:- +full:specific
1 Device-Tree bindings for Samsung SoC display controller (FIMD)
8 - compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
12 "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
13 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
14 "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
15 "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
17 - reg: physical base address and length of the FIMD registers set.
19 - interrupts: should contain a list of all FIMD IP block interrupts in the
23 - interrupt-names: should contain the interrupt names: "fifo", "vsync",
27 - pinctrl-0: pin control group to be used for this controller.
29 - pinctrl-names: must contain a "default" entry.
31 - clocks: must include clock specifiers corresponding to entries in the
32 clock-names property.
34 - clock-names: list of clock names sorted in the same order as the clocks
38 - power-domains: a phandle to FIMD power domain node.
39 - samsung,invert-vden: video enable signal is inverted
40 - samsung,invert-vclk: video clock signal is inverted
41 - display-timings: timing settings for FIMD, as described in document [1].
43 or to override timings provided by the panel.
44 - samsung,sysreg: handle to syscon used to control the system registers
45 - i80-if-timings: timing configuration for lcd i80 interface support.
46 - cs-setup: clock cycles for the active period of address signal is enabled
49 - wr-setup: clock cycles for the active period of CS signal is enabled until
52 - wr-active: clock cycles for the active period of CS is enabled.
54 - wr-hold: clock cycles for the active period of CS is disabled until write
62 Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
63 | cs-setup+1 | : : :
64 |<---------->| : : :
66 | wr-setup+1 | | wr-hold+1 |
67 |<---------->| |<---------->|
69 | wr-active+1|
70 |<---------->|
71 Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
74 in [2]. The following are properties specific to those nodes:
75 - reg: (required) port index, can be:
76 0 - for CAMIF0 input,
77 1 - for CAMIF1 input,
78 2 - for CAMIF2 input,
79 3 - for parallel output,
80 4 - for write-back interface
82 [1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
83 [2]: Documentation/devicetree/bindings/media/video-interfaces.txt
87 SoC specific DT entry:
90 compatible = "samsung,exynos4210-fimd";
91 interrupt-parent = <&combiner>;
93 interrupt-names = "fifo", "vsync", "lcd_sys";
96 clock-names = "sclk_fimd", "fimd";
97 power-domains = <&pd_lcd0>;
101 Board specific DT entry:
104 pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
105 pinctrl-names = "default";