Lines Matching +full:cache +full:-
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
27 - qcom,sdm845-cpufreq-hw
28 - qcom,sm6115-cpufreq-hw
29 - qcom,sm6350-cpufreq-hw
30 - qcom,sm8150-cpufreq-hw
31 - const: qcom,cpufreq-hw
33 - description: v2 of CPUFREQ HW (EPSS)
35 - enum:
36 - qcom,qdu1000-cpufreq-epss
37 - qcom,sa8775p-cpufreq-epss
38 - qcom,sc7280-cpufreq-epss
39 - qcom,sc8280xp-cpufreq-epss
40 - qcom,sdx75-cpufreq-epss
41 - qcom,sm6375-cpufreq-epss
42 - qcom,sm8250-cpufreq-epss
43 - qcom,sm8350-cpufreq-epss
44 - qcom,sm8450-cpufreq-epss
45 - qcom,sm8550-cpufreq-epss
46 - qcom,sm8650-cpufreq-epss
47 - const: qcom,cpufreq-epss
52 - description: Frequency domain 0 register region
53 - description: Frequency domain 1 register region
54 - description: Frequency domain 2 register region
55 - description: Frequency domain 3 register region
57 reg-names:
60 - const: freq-domain0
61 - const: freq-domain1
62 - const: freq-domain2
63 - const: freq-domain3
67 - description: XO Clock
68 - description: GPLL0 Clock
70 clock-names:
72 - const: xo
73 - const: alternate
79 interrupt-names:
82 - const: dcvsh-irq-0
83 - const: dcvsh-irq-1
84 - const: dcvsh-irq-2
85 - const: dcvsh-irq-3
87 '#freq-domain-cells':
90 '#clock-cells':
94 - compatible
95 - reg
96 - clocks
97 - clock-names
98 - '#freq-domain-cells'
103 - if:
108 - qcom,qcm2290-cpufreq-hw
115 reg-names:
123 interrupt-names:
126 - if:
131 - qcom,qdu1000-cpufreq-epss
132 - qcom,sc7180-cpufreq-hw
133 - qcom,sc8280xp-cpufreq-epss
134 - qcom,sdm670-cpufreq-hw
135 - qcom,sdm845-cpufreq-hw
136 - qcom,sm6115-cpufreq-hw
137 - qcom,sm6350-cpufreq-hw
138 - qcom,sm6375-cpufreq-epss
145 reg-names:
153 interrupt-names:
156 - if:
161 - qcom,sc7280-cpufreq-epss
162 - qcom,sm8250-cpufreq-epss
163 - qcom,sm8350-cpufreq-epss
164 - qcom,sm8450-cpufreq-epss
165 - qcom,sm8550-cpufreq-epss
172 reg-names:
180 interrupt-names:
183 - if:
188 - qcom,sm8150-cpufreq-hw
195 reg-names:
204 interrupt-names:
209 - |
210 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
211 #include <dt-bindings/clock/qcom,rpmh.h>
213 // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
216 #address-cells = <2>;
217 #size-cells = <0>;
223 enable-method = "psci";
224 next-level-cache = <&L2_0>;
225 qcom,freq-domain = <&cpufreq_hw 0>;
227 L2_0: l2-cache {
228 compatible = "cache";
229 cache-unified;
230 cache-level = <2>;
231 next-level-cache = <&L3_0>;
232 L3_0: l3-cache {
233 compatible = "cache";
234 cache-unified;
235 cache-level = <3>;
244 enable-method = "psci";
245 next-level-cache = <&L2_100>;
246 qcom,freq-domain = <&cpufreq_hw 0>;
248 L2_100: l2-cache {
249 compatible = "cache";
250 cache-unified;
251 cache-level = <2>;
252 next-level-cache = <&L3_0>;
260 enable-method = "psci";
261 next-level-cache = <&L2_200>;
262 qcom,freq-domain = <&cpufreq_hw 0>;
264 L2_200: l2-cache {
265 compatible = "cache";
266 cache-unified;
267 cache-level = <2>;
268 next-level-cache = <&L3_0>;
276 enable-method = "psci";
277 next-level-cache = <&L2_300>;
278 qcom,freq-domain = <&cpufreq_hw 0>;
280 L2_300: l2-cache {
281 compatible = "cache";
282 cache-unified;
283 cache-level = <2>;
284 next-level-cache = <&L3_0>;
292 enable-method = "psci";
293 next-level-cache = <&L2_400>;
294 qcom,freq-domain = <&cpufreq_hw 1>;
296 L2_400: l2-cache {
297 compatible = "cache";
298 cache-unified;
299 cache-level = <2>;
300 next-level-cache = <&L3_0>;
308 enable-method = "psci";
309 next-level-cache = <&L2_500>;
310 qcom,freq-domain = <&cpufreq_hw 1>;
312 L2_500: l2-cache {
313 compatible = "cache";
314 cache-unified;
315 cache-level = <2>;
316 next-level-cache = <&L3_0>;
324 enable-method = "psci";
325 next-level-cache = <&L2_600>;
326 qcom,freq-domain = <&cpufreq_hw 1>;
328 L2_600: l2-cache {
329 compatible = "cache";
330 cache-unified;
331 cache-level = <2>;
332 next-level-cache = <&L3_0>;
340 enable-method = "psci";
341 next-level-cache = <&L2_700>;
342 qcom,freq-domain = <&cpufreq_hw 1>;
344 L2_700: l2-cache {
345 compatible = "cache";
346 cache-unified;
347 cache-level = <2>;
348 next-level-cache = <&L3_0>;
354 #address-cells = <1>;
355 #size-cells = <1>;
358 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
360 reg-names = "freq-domain0", "freq-domain1";
363 clock-names = "xo", "alternate";
365 #freq-domain-cells = <1>;
366 #clock-cells = <1>;