Lines Matching +full:0 +full:x40a0
26 {2, 1641, grp_0}, /* ACH 0 */
38 {0, 0, 0}, /* FWCMDQ */
39 {0, 0, 0}, /* BMC */
40 {0, 0, 0}, /* H2D */
44 1651, /* Group 0 */
47 0, /* WP threshold */
166 .ref_rate = {R_BE_TRXPTCL_RESP_1, B_BE_WMAC_RESP_REF_RATE_SEL, 0},
173 0xf},
176 0x0},
227 [RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
228 [RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
229 [RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO] = {.offset = 0x20000, .size = 0x4800},
230 [RTW89_EFUSE_BLOCK_HCI_DIG_USB] = {.offset = 0x30000, .size = 0x890},
231 [RTW89_EFUSE_BLOCK_HCI_PHY_PCIE] = {.offset = 0x40000, .size = 0x200},
232 [RTW89_EFUSE_BLOCK_HCI_PHY_USB3] = {.offset = 0x50000, .size = 0x80},
233 [RTW89_EFUSE_BLOCK_HCI_PHY_USB2] = {.offset = 0x60000, .size = 0x0},
234 [RTW89_EFUSE_BLOCK_ADIE] = {.offset = 0x70000, .size = 0x10},
241 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
242 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
243 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
244 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
245 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
246 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x30, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
247 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
248 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
249 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x2, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
251 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
253 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
254 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
255 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
256 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
257 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x1a, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
258 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x2a, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
259 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
260 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
261 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
263 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
322 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0x02); in rtw8922a_pwr_on_func()
325 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x01, 0x01); in rtw8922a_pwr_on_func()
331 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x40, 0x40); in rtw8922a_pwr_on_func()
337 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x20, 0x20); in rtw8922a_pwr_on_func()
340 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x04, 0x04); in rtw8922a_pwr_on_func()
343 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x08, 0x08); in rtw8922a_pwr_on_func()
346 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x10); in rtw8922a_pwr_on_func()
349 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xEB, 0xFF); in rtw8922a_pwr_on_func()
352 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xEB, 0xFF); in rtw8922a_pwr_on_func()
355 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x01, 0x01); in rtw8922a_pwr_on_func()
358 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x02, 0x02); in rtw8922a_pwr_on_func()
361 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x80); in rtw8922a_pwr_on_func()
364 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF1, 0, 0x40); in rtw8922a_pwr_on_func()
367 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF2, 0, 0x40); in rtw8922a_pwr_on_func()
370 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL_1, 0x40, 0x60); in rtw8922a_pwr_on_func()
410 return 0; in rtw8922a_pwr_on_func()
418 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x10, 0x10); in rtw8922a_pwr_off_func()
421 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x08); in rtw8922a_pwr_off_func()
424 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x04); in rtw8922a_pwr_off_func()
427 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC6, 0xFF); in rtw8922a_pwr_off_func()
430 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC6, 0xFF); in rtw8922a_pwr_off_func()
433 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x80, 0x80); in rtw8922a_pwr_off_func()
436 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x02); in rtw8922a_pwr_off_func()
439 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x01); in rtw8922a_pwr_off_func()
442 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0xFF); in rtw8922a_pwr_off_func()
445 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x00, 0xFF); in rtw8922a_pwr_off_func()
458 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x20); in rtw8922a_pwr_off_func()
464 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x40); in rtw8922a_pwr_off_func()
494 rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x0000A1B2); in rtw8922a_pwr_off_func()
497 rtw89_write32(rtwdev, R_BE_UDM1, 0); in rtw8922a_pwr_off_func()
499 return 0; in rtw8922a_pwr_off_func()
513 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_efuse_parsing_tssi()
517 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) in rtw8922a_efuse_parsing_tssi()
519 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", in rtw8922a_efuse_parsing_tssi()
529 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) in rtw8922a_efuse_parsing_tssi()
531 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", in rtw8922a_efuse_parsing_tssi()
572 for (j = 0; j < RTW89_GAIN_OFFSET_NR; j++) { in rtw8922a_efuse_parsing_gain_offset()
574 if (t != 0xff) in rtw8922a_efuse_parsing_gain_offset()
576 if (t != 0x0) in rtw8922a_efuse_parsing_gain_offset()
580 if (t & 0x80) in rtw8922a_efuse_parsing_gain_offset()
581 gain->offset[i][j] = (t ^ 0x7f) + 1; in rtw8922a_efuse_parsing_gain_offset()
593 for (i = 0; i < ETH_ALEN; i += 2, addr += 2) { in rtw8922a_read_efuse_mac_addr()
595 efuse->addr[i] = val & 0xff; in rtw8922a_read_efuse_mac_addr()
605 rtw8922a_read_efuse_mac_addr(rtwdev, 0x3104); in rtw8922a_read_efuse_pci_sdio()
607 ether_addr_copy(efuse->addr, log_map + 0x001A); in rtw8922a_read_efuse_pci_sdio()
609 return 0; in rtw8922a_read_efuse_pci_sdio()
614 rtw8922a_read_efuse_mac_addr(rtwdev, 0x4078); in rtw8922a_read_efuse_usb()
616 return 0; in rtw8922a_read_efuse_usb()
626 efuse->country_code[0] = map->country_code[0]; in rtw8922a_read_efuse_rf()
633 return 0; in rtw8922a_read_efuse_rf()
647 return 0; in rtw8922a_read_efuse()
652 #define THM_TRIM_MAGNITUDE_MASK GENMASK(5, 0)
657 static const u32 thm_trim_addr[RF_PATH_NUM_8922A] = {0x1706, 0x1733}; in rtw8922a_phycap_parsing_thermal_trim()
665 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_thermal_trim()
667 if (pg_th == 0xff) { in rtw8922a_phycap_parsing_thermal_trim()
668 info->thermal_trim[i] = 0; in rtw8922a_phycap_parsing_thermal_trim()
681 "[THERMAL][TRIM] path=%d thermal_trim=0x%x (%d)\n", in rtw8922a_phycap_parsing_thermal_trim()
691 static const u32 pabias_trim_addr[RF_PATH_NUM_8922A] = {0x1707, 0x1734}; in rtw8922a_phycap_parsing_pa_bias_trim()
692 static const u32 check_pa_pad_trim_addr = 0x1700; in rtw8922a_phycap_parsing_pa_bias_trim()
699 if (val != 0xff) in rtw8922a_phycap_parsing_pa_bias_trim()
702 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_pa_bias_trim()
706 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", in rtw8922a_phycap_parsing_pa_bias_trim()
724 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_pa_bias_trim()
725 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); in rtw8922a_pa_bias_trim()
729 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", in rtw8922a_pa_bias_trim()
740 static const u32 pad_bias_trim_addr[RF_PATH_NUM_8922A] = {0x1708, 0x1735}; in rtw8922a_phycap_parsing_pad_bias_trim()
745 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_pad_bias_trim()
749 "[PAD_BIAS][TRIM] path=%d pad_bias_trim=0x%x\n", in rtw8922a_phycap_parsing_pad_bias_trim()
766 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_pad_bias_trim()
767 pad_bias_2g = u8_get_bits(info->pad_bias_trim[i], GENMASK(3, 0)); in rtw8922a_pad_bias_trim()
771 "[PAD_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", in rtw8922a_pad_bias_trim()
785 return 0; in rtw8922a_read_phycap()
801 u8 txsb20 = 0, txsb40 = 0, txsb80 = 0; in rtw8922a_set_channel_mac()
839 txsb = 0; in rtw8922a_set_channel_mac()
872 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
874 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
878 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x3f); in rtw8922a_set_channel_mac()
880 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x3e); in rtw8922a_set_channel_mac()
886 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
887 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
891 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
892 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
913 return 0; in rtw8922a_ctrl_sco_cck()
924 { .addr = 0x41E8, .mask = 0xFF00},
925 { .addr = 0x41E8, .mask = 0xFF0000},
926 { .addr = 0x41E8, .mask = 0xFF000000},
927 { .addr = 0x41EC, .mask = 0xFF},
928 { .addr = 0x41EC, .mask = 0xFF00},
929 { .addr = 0x41EC, .mask = 0xFF0000},
930 { .addr = 0x41EC, .mask = 0xFF000000},
931 { .addr = 0x41F0, .mask = 0xFF}
935 { .addr = 0x41F4, .mask = 0xFF},
936 { .addr = 0x41F4, .mask = 0xFF00},
937 { .addr = 0x41F4, .mask = 0xFF0000},
938 { .addr = 0x41F4, .mask = 0xFF000000}
942 { .addr = 0x41F0, .mask = 0xFF0000},
943 { .addr = 0x41F0, .mask = 0xFF000000}
947 { .addr = 0x41F0, .mask = 0xFF00}
951 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
952 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
953 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
954 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
955 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
956 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
957 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
958 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
959 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
960 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
961 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
962 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
963 { .gain_g = {0x40a8, 0x44a8}, .gain_a = {0x4078, 0x4478},
964 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
968 { .gain_g = {0x4054, 0x4454}, .gain_a = {0x4054, 0x4454},
969 .gain_g_mask = 0x7FC0000, .gain_a_mask = 0x1FF},
970 { .gain_g = {0x4058, 0x4458}, .gain_a = {0x4054, 0x4454},
971 .gain_g_mask = 0x1FF, .gain_a_mask = 0x3FE00 },
975 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x4078, 0x4478},
976 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
977 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x407c, 0x447c},
978 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
979 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x407c, 0x447c},
980 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
981 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x407c, 0x447c},
982 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF0000},
983 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x407c, 0x447c},
984 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
985 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x4080, 0x4480},
986 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
987 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x4080, 0x4480},
988 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
992 { .gain_g = {0x40b4, 0x44b4}, .gain_a = {0x4080, 0x4480},
993 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
994 { .gain_g = {0x40b4, 0x44b4}, .gain_a = {0x4084, 0x4484},
995 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
996 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
997 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
998 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
999 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1000 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
1001 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
1002 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4088, 0x4488},
1003 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
1004 { .gain_g = {0x40bc, 0x44bc}, .gain_a = {0x4088, 0x4488},
1005 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
1006 { .gain_g = {0x40bc, 0x44bc}, .gain_a = {0x4088, 0x4488},
1007 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1024 u32 reg_path_ofst = 0; in rtw8922a_set_rpl_gain()
1031 reg_path_ofst = 0x400; in rtw8922a_set_rpl_gain()
1033 for (i = 0; i < RTW89_BW20_SC_160M; i++) { in rtw8922a_set_rpl_gain()
1040 for (i = 0; i < RTW89_BW20_SC_80M; i++) { in rtw8922a_set_rpl_gain()
1047 for (i = 0; i < RTW89_BW20_SC_40M; i++) { in rtw8922a_set_rpl_gain()
1054 for (i = 0; i < RTW89_BW20_SC_20M; i++) { in rtw8922a_set_rpl_gain()
1078 for (i = 0; i < LNA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1090 for (i = 0; i < TIA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1102 for (i = 0; i < LNA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1114 for (i = 0; i < TIA_LNA_OP1DB_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1142 u8 fraction = value & 0x3; in rtw8922a_set_rx_gain_normal_cck()
1146 (0x4 - fraction) << 1); in rtw8922a_set_rx_gain_normal_cck()
1148 (0x4 - fraction) << 1); in rtw8922a_set_rx_gain_normal_cck()
1152 value + 1 + 0xdc); in rtw8922a_set_rx_gain_normal_cck()
1154 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW20, 0); in rtw8922a_set_rx_gain_normal_cck()
1155 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW40, 0); in rtw8922a_set_rx_gain_normal_cck()
1159 value + 0xdc); in rtw8922a_set_rx_gain_normal_cck()
1167 static const u32 rssi_tb_bias_comp[2] = {0x41f8, 0x45f8}; in rtw8922a_set_rx_gain_normal_ofdm()
1168 static const u32 rssi_tb_ext_comp[2] = {0x4208, 0x4608}; in rtw8922a_set_rx_gain_normal_ofdm()
1169 static const u32 rssi_ofst_addr[2] = {0x40c8, 0x44c8}; in rtw8922a_set_rx_gain_normal_ofdm()
1170 static const u32 rpl_bias_comp[2] = {0x41e8, 0x45e8}; in rtw8922a_set_rx_gain_normal_ofdm()
1171 static const u32 rpl_ext_comp[2] = {0x41f8, 0x45f8}; in rtw8922a_set_rx_gain_normal_ofdm()
1179 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], 0xff000000, value + 0xF8); in rtw8922a_set_rx_gain_normal_ofdm()
1188 rtw89_phy_write32_mask(rtwdev, rpl_bias_comp[path], 0xff, v1); in rtw8922a_set_rx_gain_normal_ofdm()
1189 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff, v2); in rtw8922a_set_rx_gain_normal_ofdm()
1190 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff00, v3); in rtw8922a_set_rx_gain_normal_ofdm()
1192 rtw89_phy_write32_mask(rtwdev, rssi_tb_bias_comp[path], 0xff0000, v1); in rtw8922a_set_rx_gain_normal_ofdm()
1193 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff0000, v2); in rtw8922a_set_rx_gain_normal_ofdm()
1194 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff000000, v3); in rtw8922a_set_rx_gain_normal_ofdm()
1216 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3b13ff, phy_idx); in rtw8922a_set_cck_parameters()
1217 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x1c42de, phy_idx); in rtw8922a_set_cck_parameters()
1218 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0xfdb0ad, phy_idx); in rtw8922a_set_cck_parameters()
1219 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0xf60f6e, phy_idx); in rtw8922a_set_cck_parameters()
1220 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfd8f92, phy_idx); in rtw8922a_set_cck_parameters()
1221 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0x02d011, phy_idx); in rtw8922a_set_cck_parameters()
1222 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0x01c02c, phy_idx); in rtw8922a_set_cck_parameters()
1223 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xfff00a, phy_idx); in rtw8922a_set_cck_parameters()
1225 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3a63ca, phy_idx); in rtw8922a_set_cck_parameters()
1226 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x2a833f, phy_idx); in rtw8922a_set_cck_parameters()
1227 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0x1491f8, phy_idx); in rtw8922a_set_cck_parameters()
1228 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0x03c0b0, phy_idx); in rtw8922a_set_cck_parameters()
1229 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfccff1, phy_idx); in rtw8922a_set_cck_parameters()
1230 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0xfccfc3, phy_idx); in rtw8922a_set_cck_parameters()
1231 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0xfebfdc, phy_idx); in rtw8922a_set_cck_parameters()
1232 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xffdff7, phy_idx); in rtw8922a_set_cck_parameters()
1240 static const u32 band_sel[2] = {0x4160, 0x4560}; in rtw8922a_ctrl_ch()
1280 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1281 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1282 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1283 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1284 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1285 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1288 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1289 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x2, phy_idx); in rtw8922a_ctrl_bw()
1290 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1291 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1292 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1293 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1296 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1297 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1298 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1299 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1300 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1301 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1304 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1305 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1307 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1308 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1309 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1312 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x2, phy_idx); in rtw8922a_ctrl_bw()
1313 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1315 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1316 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1317 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1320 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x3, phy_idx); in rtw8922a_ctrl_bw()
1321 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1323 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1324 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1325 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1336 rtw89_phy_write32_idx(rtwdev, R_FC0, B_BW40_2XFFT, 0, phy_idx); in rtw8922a_ctrl_bw()
1342 return 0; in rtw8922a_spur_freq()
1357 if (spur_freq == 0) { in rtw8922a_set_csi_tone_idx()
1359 0, phy_idx); in rtw8922a_set_csi_tone_idx()
1374 .notch1_idx = {0x41a0, 0xFF},
1375 .notch1_frac_idx = {0x41a0, 0xC00},
1376 .notch1_en = {0x41a0, 0x1000},
1377 .notch2_idx = {0x41ac, 0xFF},
1378 .notch2_frac_idx = {0x41ac, 0xC00},
1379 .notch2_en = {0x41ac, 0x1000},
1382 .notch1_idx = {0x45a0, 0xFF},
1383 .notch1_frac_idx = {0x45a0, 0xC00},
1384 .notch1_en = {0x45a0, 0x1000},
1385 .notch2_idx = {0x45ac, 0xFF},
1386 .notch2_frac_idx = {0x45ac, 0xC00},
1387 .notch2_en = {0x45ac, 0x1000},
1404 if (spur_freq == 0) { in rtw8922a_set_nbi_tone_idx()
1406 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1408 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1444 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1448 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1456 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1460 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1476 u32 cr_ofst = 0x0; in rtw8922a_ctrl_afe_dac()
1479 cr_ofst = 0x100; in rtw8922a_ctrl_afe_dac()
1487 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xE); in rtw8922a_ctrl_afe_dac()
1488 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x7); in rtw8922a_ctrl_afe_dac()
1491 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xD); in rtw8922a_ctrl_afe_dac()
1492 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x6); in rtw8922a_ctrl_afe_dac()
1500 {0x6990, 0x00000000},
1501 {0x6994, 0x00000000},
1502 {0x6998, 0x00000000},
1503 {0x6820, 0xFFFFFFFE},
1504 {0x6800, 0xC0000FFE},
1505 {0x6808, 0x76543210},
1506 {0x6814, 0xBFBFB000},
1507 {0x6818, 0x0478C009},
1508 {0x6800, 0xC0000FFF},
1509 {0x6820, 0xFFFFFFFF},
1513 {0x6990, 0x00000000},
1514 {0x6994, 0x00000000},
1515 {0x6998, 0x00000000},
1516 {0x6820, 0xFFFFFFFE},
1517 {0x6800, 0xC0000FFE},
1518 {0x6808, 0x76543210},
1519 {0x6814, 0xBFBFB000},
1520 {0x6818, 0x0478C009},
1521 {0x6800, 0xC0000FFF},
1522 {0x6820, 0xFFFFFFFF},
1539 for (i = 0; i < size; i++, reg++) in rtw8922a_bbmcu_cr_init()
1550 u32 rdy = 0; in rtw8922a_bb_preinit()
1555 rtw89_write32_mask(rtwdev, R_BE_DMAC_SYS_CR32B, dmac_sys_mask[phy_idx], 0x7FF9); in rtw8922a_bb_preinit()
1556 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1557 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1558 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1); in rtw8922a_bb_preinit()
1560 rtw89_write32_mask(rtwdev, R_BE_MEM_PWR_CTRL, B_BE_MEM_BBMCU0_DS_V1, 0); in rtw8922a_bb_preinit()
1574 rtw89_phy_set_phy_regs(rtwdev, R_TXFCTR, B_TXFCTR_THD, 0x200); in rtw8922a_bb_postinit()
1575 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_EHT_RATE_TH, 0xA); in rtw8922a_bb_postinit()
1576 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_HE_RATE_TH, 0xA); in rtw8922a_bb_postinit()
1577 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_HT_VHT_TH, 0xAAA); in rtw8922a_bb_postinit()
1578 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_EHT_MCS14, 0x1); in rtw8922a_bb_postinit()
1579 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_EHT_MCS15, 0x1); in rtw8922a_bb_postinit()
1580 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_EHTTB_EN, 0x0); in rtw8922a_bb_postinit()
1581 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEERSU_EN, 0x0); in rtw8922a_bb_postinit()
1582 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEMU_EN, 0x0); in rtw8922a_bb_postinit()
1583 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_TB_EN, 0x0); in rtw8922a_bb_postinit()
1584 rtw89_phy_set_phy_regs(rtwdev, R_SU_PUNC, B_SU_PUNC_EN, 0x1); in rtw8922a_bb_postinit()
1585 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_HWGEN_EN, 0x1); in rtw8922a_bb_postinit()
1586 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_PWROFST_COMP, 0x1); in rtw8922a_bb_postinit()
1587 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_BY_SLOPE, 0x1); in rtw8922a_bb_postinit()
1588 rtw89_phy_set_phy_regs(rtwdev, R_MAG_A, B_MGA_AEND, 0xe0); in rtw8922a_bb_postinit()
1589 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_MAG_AB, 0xe0c000); in rtw8922a_bb_postinit()
1590 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_A, 0x3FE0); in rtw8922a_bb_postinit()
1591 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_B, 0x3FE0); in rtw8922a_bb_postinit()
1592 rtw89_phy_set_phy_regs(rtwdev, R_SC_CORNER, B_SC_CORNER, 0x200); in rtw8922a_bb_postinit()
1593 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x0, phy_idx); in rtw8922a_bb_postinit()
1594 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x1, phy_idx); in rtw8922a_bb_postinit()
1604 B_RXCCA_BE1_DIS, 0x0, phy_idx); in rtw8922a_bb_reset_en()
1605 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0, phy_idx); in rtw8922a_bb_reset_en()
1607 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0x1, phy_idx); in rtw8922a_bb_reset_en()
1608 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1, phy_idx); in rtw8922a_bb_reset_en()
1610 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); in rtw8922a_bb_reset_en()
1619 {0x11A00, 0x21C86900}, in rtw8922a_ctrl_tx_path_tmac()
1620 {0x11A04, 0x00E4E433}, in rtw8922a_ctrl_tx_path_tmac()
1621 {0x11A08, 0x39390CC9}, in rtw8922a_ctrl_tx_path_tmac()
1622 {0x11A0C, 0x4E433240}, in rtw8922a_ctrl_tx_path_tmac()
1623 {0x11A10, 0x90CC900E}, in rtw8922a_ctrl_tx_path_tmac()
1624 {0x11A14, 0x00240393}, in rtw8922a_ctrl_tx_path_tmac()
1625 {0x11A18, 0x201C8600}, in rtw8922a_ctrl_tx_path_tmac()
1627 int ret = 0; in rtw8922a_ctrl_tx_path_tmac()
1631 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL, 0x0, phy_idx); in rtw8922a_ctrl_tx_path_tmac()
1634 return 0; in rtw8922a_ctrl_tx_path_tmac()
1637 path_com_cr[0].data = 0x21C82900; in rtw8922a_ctrl_tx_path_tmac()
1638 path_com_cr[1].data = 0x00E4E431; in rtw8922a_ctrl_tx_path_tmac()
1639 path_com_cr[2].data = 0x39390C49; in rtw8922a_ctrl_tx_path_tmac()
1640 path_com_cr[3].data = 0x4E431240; in rtw8922a_ctrl_tx_path_tmac()
1641 path_com_cr[4].data = 0x90C4900E; in rtw8922a_ctrl_tx_path_tmac()
1642 path_com_cr[6].data = 0x201C8200; in rtw8922a_ctrl_tx_path_tmac()
1644 path_com_cr[0].data = 0x21C04900; in rtw8922a_ctrl_tx_path_tmac()
1645 path_com_cr[1].data = 0x00E4E032; in rtw8922a_ctrl_tx_path_tmac()
1646 path_com_cr[2].data = 0x39380C89; in rtw8922a_ctrl_tx_path_tmac()
1647 path_com_cr[3].data = 0x4E032240; in rtw8922a_ctrl_tx_path_tmac()
1648 path_com_cr[4].data = 0x80C8900E; in rtw8922a_ctrl_tx_path_tmac()
1649 path_com_cr[6].data = 0x201C0400; in rtw8922a_ctrl_tx_path_tmac()
1651 path_com_cr[0].data = 0x21C86900; in rtw8922a_ctrl_tx_path_tmac()
1652 path_com_cr[1].data = 0x00E4E433; in rtw8922a_ctrl_tx_path_tmac()
1653 path_com_cr[2].data = 0x39390CC9; in rtw8922a_ctrl_tx_path_tmac()
1654 path_com_cr[3].data = 0x4E433240; in rtw8922a_ctrl_tx_path_tmac()
1655 path_com_cr[4].data = 0x90CC900E; in rtw8922a_ctrl_tx_path_tmac()
1656 path_com_cr[6].data = 0x201C8600; in rtw8922a_ctrl_tx_path_tmac()
1661 for (i = 0; i < ARRAY_SIZE(path_com_cr); i++) { in rtw8922a_ctrl_tx_path_tmac()
1677 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_HTMCS_LMT, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1678 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_VHTMCS_LMT, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1681 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1682 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_TB_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1683 rtw89_phy_write32_idx(rtwdev, R_BRK_EHT, B_RXEHT_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1684 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHTTB_NSS_MAX, 0, in rtw8922a_cfg_rx_nss_limit()
1704 return 0; in rtw8922a_cfg_rx_nss_limit()
1713 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0); in rtw8922a_tssi_reset()
1714 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1); in rtw8922a_tssi_reset()
1716 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0); in rtw8922a_tssi_reset()
1717 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1); in rtw8922a_tssi_reset()
1720 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0); in rtw8922a_tssi_reset()
1721 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1); in rtw8922a_tssi_reset()
1722 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0); in rtw8922a_tssi_reset()
1723 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1); in rtw8922a_tssi_reset()
1733 /* Set to 0 first to avoid abnormal EDCCA report */ in rtw8922a_ctrl_rx_path_tmac()
1734 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x0, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1737 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x1, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1742 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x2, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1747 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x3, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1755 return 0; in rtw8922a_ctrl_rx_path_tmac()
1760 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
1761 0x0BB80708, 0x17701194, 0x02020100, 0x03030303, 0x01000303,
1762 0x05030302, 0x06060605, 0x06050300, 0x0A090807, 0x02000B0B,
1763 0x09080604, 0x0D0D0C0B, 0x08060400, 0x110F0C0B, 0x05001111,
1764 0x0D0C0907, 0x12121210},
1765 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
1766 0x0BB80708, 0x17701194, 0x04030201, 0x05050505, 0x01000505,
1767 0x07060504, 0x09090908, 0x09070400, 0x0E0D0C0B, 0x03000E0E,
1768 0x0D0B0907, 0x1010100F, 0x0B080500, 0x1512100D, 0x05001515,
1769 0x100D0B08, 0x15151512},
1782 digital_pwr_comp = rtw8922a_digital_pwr_comp_val[0]; in rtw8922a_set_digital_pwr_comp()
1787 for (i = 0; i < DIGITAL_PWR_COMP_REG_NUM; i++, addr += 4) { in rtw8922a_set_digital_pwr_comp()
1788 val = enable ? digital_pwr_comp[i] : 0; in rtw8922a_set_digital_pwr_comp()
1817 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x1); in rtw8922a_ctrl_mlo()
1818 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x0); in rtw8922a_ctrl_mlo()
1821 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_ctrl_mlo()
1822 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x1); in rtw8922a_ctrl_mlo()
1828 chan0 = rtw89_mgnt_chan_get(rtwdev, 0); in rtw8922a_ctrl_mlo()
1834 chan0 = rtw89_mgnt_chan_get(rtwdev, 0); in rtw8922a_ctrl_mlo()
1841 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180); in rtw8922a_ctrl_mlo()
1844 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_ctrl_mlo()
1845 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9); in rtw8922a_ctrl_mlo()
1846 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9); in rtw8922a_ctrl_mlo()
1847 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9); in rtw8922a_ctrl_mlo()
1849 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_ctrl_mlo()
1850 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF); in rtw8922a_ctrl_mlo()
1851 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF); in rtw8922a_ctrl_mlo()
1852 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF); in rtw8922a_ctrl_mlo()
1854 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x7BAB); in rtw8922a_ctrl_mlo()
1855 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3BAB); in rtw8922a_ctrl_mlo()
1856 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3AAB); in rtw8922a_ctrl_mlo()
1858 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x180); in rtw8922a_ctrl_mlo()
1859 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x0); in rtw8922a_ctrl_mlo()
1862 return 0; in rtw8922a_ctrl_mlo()
1872 rtw89_write32_mask(rtwdev, R_BE_PWR_BOOST, B_BE_PWR_CTRL_SEL, 0); in rtw8922a_bb_sethw()
1875 rtw89_write32_mask(rtwdev, reg, B_BE_PWR_CTRL_SEL, 0); in rtw8922a_bb_sethw()
1885 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0, phy_idx); in rtw8922a_ctrl_cck_en()
1888 0, phy_idx); in rtw8922a_ctrl_cck_en()
1891 rtw89_phy_write32_idx(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0, phy_idx); in rtw8922a_ctrl_cck_en()
1924 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_pre_set_channel_bb()
1925 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180); in rtw8922a_pre_set_channel_bb()
1926 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_pre_set_channel_bb()
1927 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9); in rtw8922a_pre_set_channel_bb()
1928 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9); in rtw8922a_pre_set_channel_bb()
1929 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9); in rtw8922a_pre_set_channel_bb()
1931 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_pre_set_channel_bb()
1932 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_pre_set_channel_bb()
1933 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF); in rtw8922a_pre_set_channel_bb()
1934 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF); in rtw8922a_pre_set_channel_bb()
1935 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF); in rtw8922a_pre_set_channel_bb()
1964 u32 path_ofst = (path == RF_PATH_B) ? 0x100 : 0x0; in rtw8922a_dfs_en_idx()
1967 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 1, in rtw8922a_dfs_en_idx()
1970 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 0, in rtw8922a_dfs_en_idx()
1990 val &= ~0x1; in rtw8922a_adc_en_path()
1992 val &= ~0x2; in rtw8922a_adc_en_path()
1995 val |= 0x1; in rtw8922a_adc_en_path()
1997 val |= 0x2; in rtw8922a_adc_en_path()
2064 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); in rtw8922a_rfk_init()
2093 for (path = 0; path < RF_PATH_NUM_8922A; path++) { in _wait_rx_mode()
2098 2, 5000, false, rtwdev, path, 0x00, in _wait_rx_mode()
2150 s16 ref_ofdm = 0; in rtw8922a_set_txpwr_ref()
2151 s16 ref_cck = 0; in rtw8922a_set_txpwr_ref()
2178 static const u32 path_ofst[] = {0x0, 0x100}; in rtw8922a_set_txpwr_diff()
2180 static const s16 tssi_k_base = 0x12; in rtw8922a_set_txpwr_diff()
2185 s16 pwr_ref = 0; in rtw8922a_set_txpwr_diff()
2194 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? pwr_ref : pwr_ref_ofst; in rtw8922a_set_txpwr_diff()
2195 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ref_ofst : pwr_ref; in rtw8922a_set_txpwr_diff()
2196 tssi_k[RF_PATH_A] = pwr_ofst > 0 ? tssi_k_base : tssi_k_ofst; in rtw8922a_set_txpwr_diff()
2197 tssi_k[RF_PATH_B] = pwr_ofst > 0 ? tssi_k_ofst : tssi_k_base; in rtw8922a_set_txpwr_diff()
2199 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_set_txpwr_diff()
2202 rtw89_phy_write32_mask(rtwdev, txpwr_ref[0].addr + path_ofst[i], in rtw8922a_set_txpwr_diff()
2203 txpwr_ref[0].mask, ofst_dec[i]); in rtw8922a_set_txpwr_diff()
2214 u8 ctrl = en ? 0x1 : 0x0; in rtw8922a_bb_tx_triangular()
2232 if (tx_shape_idx == 0) in rtw8922a_set_tx_shape()
2300 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x3, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2302 0xf, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2304 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2305 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2306 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x80, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2307 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x8080, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2308 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2309 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2310 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x3, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2312 0xf, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2314 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2315 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2316 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x80, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2317 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x8080, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2318 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2319 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2321 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2323 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2325 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2326 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2327 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x1a, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2328 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x2a2a, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2329 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x7a6, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2330 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x26, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2331 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2333 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2335 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2336 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2337 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2338 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x2a30, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2339 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x7a6, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2340 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x26, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2381 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); in rtw8922a_get_thermal()
2382 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); in rtw8922a_get_thermal()
2383 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); in rtw8922a_get_thermal()
2390 return clamp_t(int, th, 0, U8_MAX); in rtw8922a_get_thermal()
2442 module->bt_solo = 0; in rtw8922a_btc_set_rfe()
2444 module->wa_type = 0; in rtw8922a_btc_set_rfe()
2449 module->ant.diversity = 0; in rtw8922a_btc_set_rfe()
2458 if (module->rfe_type == 0) { in rtw8922a_btc_set_rfe()
2465 if (module->kt_ver == 0) in rtw8922a_btc_set_rfe()
2508 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */ in rtw8922a_btc_init_cfg()
2509 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff); in rtw8922a_btc_init_cfg()
2511 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */ in rtw8922a_btc_init_cfg()
2512 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df); in rtw8922a_btc_init_cfg()
2514 /* if GNT_WL = 0 && BT = Tx_group --> in rtw8922a_btc_init_cfg()
2515 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff) in rtw8922a_btc_init_cfg()
2518 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f); in rtw8922a_btc_init_cfg()
2520 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff); in rtw8922a_btc_init_cfg()
2522 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0); in rtw8922a_btc_init_cfg()
2534 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_0, 0xda5a5a5a); in rtw8922a_btc_init_cfg()
2536 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_1, 0xda5a5a5a); in rtw8922a_btc_init_cfg()
2538 rtw89_write32(rtwdev, R_BTC_ZB_BREAK_TBL, 0xf0ffffff); in rtw8922a_btc_init_cfg()
2545 u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0)); in rtw8922a_btc_set_wl_txpwr_ctrl()
2549 case 0xffff: in rtw8922a_btc_set_wl_txpwr_ctrl()
2551 B_BE_FORCE_PWR_BY_RATE_EN, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2553 B_BE_FORCE_PWR_BY_RATE_VAL, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2559 B_BE_FORCE_PWR_BY_RATE_EN, 0x1); in rtw8922a_btc_set_wl_txpwr_ctrl()
2564 case 0xffff: in rtw8922a_btc_set_wl_txpwr_ctrl()
2566 B_BE_PWR_BT_EN, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2568 B_BE_PWR_BT_VAL, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2574 B_BE_PWR_BT_EN, 0x1); in rtw8922a_btc_set_wl_txpwr_ctrl()
2582 return clamp_t(s8, val, -100, 0) + 100; in rtw8922a_btc_get_bt_rssi()
2586 {255, 0, 0, 7}, /* 0 -> original */
2587 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2588 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2589 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2590 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2591 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2592 {6, 1, 0, 7},
2593 {13, 1, 0, 7},
2594 {13, 1, 0, 7}
2598 {255, 0, 0, 7}, /* 0 -> original */
2599 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2600 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2601 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2602 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2603 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2604 {255, 1, 0, 7},
2605 {255, 1, 0, 7},
2606 {255, 1, 0, 7}
2613 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe300),
2614 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe320),
2615 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe324),
2616 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe328),
2617 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe32c),
2618 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe330),
2619 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe334),
2620 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe338),
2621 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe344),
2622 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe348),
2623 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe34c),
2624 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe350),
2625 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a2c),
2626 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a50),
2627 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2628 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x660),
2629 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x1660),
2630 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x418c),
2631 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x518c),
2644 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2645 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2646 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2647 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x01018); in rtw8922a_btc_wl_s1_standby()
2648 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2650 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2651 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2652 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2653 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x01018); in rtw8922a_btc_wl_s1_standby()
2654 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2656 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2657 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2658 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2659 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x09018); in rtw8922a_btc_wl_s1_standby()
2660 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2662 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2663 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2664 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2665 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x09018); in rtw8922a_btc_wl_s1_standby()
2666 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2682 if (chan_idx == 0) in rtw8922a_fill_freq_with_ppdu()
2701 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { in rtw8922a_query_ppdu()
2713 static const u8 bw_compensate[] = {0, 0, 0, 6, 12, 18, 0}; in rtw8922a_convert_rpl_to_rssi()
2715 u8 compensate = 0; in rtw8922a_convert_rpl_to_rssi()
2722 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_convert_rpl_to_rssi()
2724 rssi[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2725 phy_ppdu->rpl_path[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2726 phy_ppdu->rpl_fd[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2745 if (desc_info->rssi <= 0x1 || (desc_info->rssi >> 2) > MAX_RSSI) in rtw8922a_phy_rpt_to_rssi()
2755 rtw89_write32(rtwdev, R_BE_DMAC_SYS_CR32B, 0x7FF97FF9); in rtw8922a_mac_enable_bb_rf()
2757 return 0; in rtw8922a_mac_enable_bb_rf()
2765 return 0; in rtw8922a_mac_disable_bb_rf()
2859 .dle_scc_rsvd_size = 0,
2862 .rsvd_ple_ofst = 0x8f800,
2867 .rf_base_addr = {0xe000, 0xf000},
2868 .thermal_th = {0xad, 0xb4},
2917 .physical_efuse_size = 0x1300,
2918 .logical_efuse_size = 0x70000,
2919 .limit_efuse_size = 0x40000,
2920 .dav_phy_efuse_size = 0,
2921 .dav_log_efuse_size = 0,
2923 .phycap_addr = 0x1700,
2924 .phycap_size = 0x38,
2925 .para_ver = 0xf,
2926 .wlcx_desired = 0x07110000,
2927 .scbd = 0x1,
2928 .mailbox = 0x1,
2943 .low_power_hci_modes = 0,
2960 .dcfo_comp_sft = 0,
2969 .dma_ch_mask = 0,
2980 .fw_min_ver_code = RTW89_FW_VER_CODE(0, 35, 54, 0),