Lines Matching +full:0 +full:xe94
19 #define WLAN_SLOT_TIME 0x09
20 #define WLAN_RL_VAL 0x3030
21 #define WLAN_BAR_VAL 0x0201ffff
22 #define BIT_MASK_TBTT_HOLD 0x00000fff
24 #define BIT_MASK_TBTT_SETUP 0x000000ff
25 #define BIT_SHIFT_TBTT_SETUP 0
30 #define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80)
31 #define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64)
32 #define WLAN_PIFS_VAL 0
33 #define WLAN_AGG_BRK_TIME 0x16
34 #define WLAN_NAV_PROT_LEN 0x0040
35 #define WLAN_SPEC_SIFS 0x100a
36 #define WLAN_RX_PKT_LIMIT 0x17
37 #define WLAN_MAX_AGG_NR 0x0A
38 #define WLAN_AMPDU_MAX_TIME 0x1C
39 #define WLAN_ANT_SEL 0x82
40 #define WLAN_LTR_IDLE_LAT 0x90039003
41 #define WLAN_LTR_ACT_LAT 0x883c883c
42 #define WLAN_LTR_CTRL1 0xCB004010
43 #define WLAN_LTR_CTRL2 0x01233425
46 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c,
47 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056,
48 0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079,
49 0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab,
50 0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2,
51 0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155,
52 0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2,
53 0x7f8001fe,
57 0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158,
58 0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263,
59 0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F,
60 0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C,
61 0x7FF,
76 dm_info->delta_power_index[path] = 0;
81 dm_info->txagc_remnant_cck = 0;
82 dm_info->txagc_remnant_ofdm = 0;
95 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);
104 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
119 rtw_write8(rtwdev, REG_ATIMWND, 0x2);
144 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
150 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
151 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
184 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0)
205 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64);
206 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */
215 page = *phy_status & 0xf;
218 case 0:
238 memset(pkt_stat, 0, sizeof(*pkt_stat));
251 pkt_stat->ppdu_cnt = 0;
301 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
302 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
303 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
304 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
305 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
306 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
307 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
313 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
314 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
315 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000);
316 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
317 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
318 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
319 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
322 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);
323 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
324 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
325 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
326 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
327 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000);
328 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
331 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
332 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
381 [0] = {
382 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C },
383 { .len = 4, .reg = 0xA28, .val = 0x00008810 },
384 { .len = 4, .reg = 0xAAC, .val = 0x01235667 },
387 { .len = 4, .reg = 0xA24, .val = 0x0000B81C },
388 { .len = 4, .reg = 0xA28, .val = 0x00000000 },
389 { .len = 4, .reg = 0xAAC, .val = 0x00003667 },
399 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];
401 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++)
406 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);
407 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);
409 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa);
412 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);
413 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);
414 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0);
416 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
452 .val_bb_sel_btg = 0x99000000,
454 .val_txiqk_pi = 0x8214019f,
458 .val_wlint = 0xe0d,
459 .val_wlsel = 0x60d,
460 .val_iqkpts = 0xfa000000,
464 .val_bb_sel_btg = 0x99000280,
466 .val_txiqk_pi = 0x8214018a,
470 .val_wlint = 0xe6d,
471 .val_wlsel = 0x66d,
472 .val_iqkpts = 0xf9000000,
482 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n",
484 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n",
488 "[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
489 rtw_read32(rtwdev, 0xe90),
490 rtw_read32(rtwdev, 0xe98));
502 return 0;
511 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n",
516 "[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
517 rtw_read32(rtwdev, 0xea0),
518 rtw_read32(rtwdev, 0xea8));
532 return 0;
535 #define IQK_LTE_WRITE_VAL_8723D 0x0000ff00
540 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000);
546 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054);
548 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n",
551 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n",
557 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000);
574 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0);
575 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0);
576 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0);
586 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n",
593 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);
594 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004);
595 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d);
596 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0);
597 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
600 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c);
601 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
603 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200);
604 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
605 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
608 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911);
611 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);
612 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);
613 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3);
614 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf);
617 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1);
618 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1);
623 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n",
626 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n",
647 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n",
655 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
656 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
659 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);
660 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
661 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
662 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
663 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000);
664 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000);
667 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911);
670 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);
671 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006);
672 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);
673 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb);
674 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
676 /* PA/PAD=0 */
677 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);
678 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);
682 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n",
685 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n",
700 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n",
706 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n",
710 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
711 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c);
712 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c);
713 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
714 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
715 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000);
716 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400);
719 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1);
724 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1);
725 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007);
726 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);
727 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb);
728 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
730 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n",
733 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n",
754 if (result[IQK_S1_TX_X] == 0)
777 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n",
780 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c);
782 if (result[IQK_S1_RX_X] == 0)
801 if (result[IQK_S0_TX_X] == 0)
818 if (result[IQK_S0_RX_X] == 0)
829 rtw_write8(rtwdev, REG_TXPAUSE, 0xff);
840 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000);
844 #define ADDA_ON_VAL_8723D 0x03c00016
855 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
856 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
876 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);
877 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611);
878 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4);
879 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200);
882 for (i = 0; i < PATH_IQK_RETRY; i++) {
895 result[t][IQK_S1_TX_X] = 0x100;
896 result[t][IQK_S1_TX_Y] = 0x0;
899 for (i = 0; i < PATH_IQK_RETRY; i++) {
912 result[t][IQK_S1_RX_X] = 0x100;
913 result[t][IQK_S1_RX_Y] = 0x0;
916 if (s1_ok == 0x0)
921 for (i = 0; i < PATH_IQK_RETRY; i++) {
934 result[t][IQK_S0_TX_X] = 0x100;
935 result[t][IQK_S0_TX_Y] = 0x0;
938 for (i = 0; i < PATH_IQK_RETRY; i++) {
952 result[t][IQK_S0_RX_X] = 0x100;
953 result[t][IQK_S0_RX_Y] = 0x0;
956 if (s0_ok == 0x0)
977 memset(result, 0, sizeof(result));
1008 s32 reg_tmp = 0;
1010 for (i = 0; i < IQK_NR; i++)
1013 if (reg_tmp != 0) {
1041 result[i][0], result[i][1], result[i][2], result[i][3],
1046 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",
1052 "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",
1075 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1083 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1084 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1095 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0);
1096 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0);
1097 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0);
1098 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0);
1099 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0);
1100 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0);
1101 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0);
1102 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0);
1113 coex_rfe->ant_switch_polarity = 0;
1122 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80);
1124 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200);
1127 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280);
1129 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0);
1133 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
1134 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1135 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1142 static const u8 wl_tx_power[] = {0xb2, 0x90};
1164 0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101,
1165 0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101,
1166 0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101,
1167 0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001,
1168 0xcd260001, 0xcc270001, 0x8f280001
1172 0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101,
1173 0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101,
1174 0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101,
1175 0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101,
1176 0x44260101, 0x43270101, 0x42280101
1186 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
1189 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
1229 /* write new elements A, C, D, and element B is always 0 */
1242 /* write new elements A, C, D, and element B is always 0 */
1266 else if (ofdm_index < 0)
1267 ofdm_index = 0;
1281 0x00);
1297 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0);
1298 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0);
1299 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0);
1322 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF,
1345 else if (final_ofdm_swing_index < 0)
1346 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0,
1349 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0);
1354 else if (final_cck_swing_index < 0)
1355 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0,
1358 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0);
1372 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1375 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1394 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1419 if (efuse->power_track_type != 0)
1424 GENMASK(17, 16), 0x03);
1466 {0xffffffff, 0xffffffff}, /* case-0 */
1467 {0x55555555, 0x55555555},
1468 {0x66555555, 0x66555555},
1469 {0xaaaaaaaa, 0xaaaaaaaa},
1470 {0x5a5a5a5a, 0x5a5a5a5a},
1471 {0xfafafafa, 0xfafafafa}, /* case-5 */
1472 {0x6a5a5555, 0xaaaaaaaa},
1473 {0x6a5a56aa, 0x6a5a56aa},
1474 {0x6a5a5a5a, 0x6a5a5a5a},
1475 {0x66555555, 0x5a5a5a5a},
1476 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1477 {0x66555555, 0x6a5a5aaa},
1478 {0x66555555, 0x5a5a5aaa},
1479 {0x66555555, 0x6aaa5aaa},
1480 {0x66555555, 0xaaaa5aaa},
1481 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1482 {0xffff55ff, 0xfafafafa},
1483 {0xffff55ff, 0x6afa5afa},
1484 {0xaaffffaa, 0xfafafafa},
1485 {0xaa5555aa, 0x5a5a5a5a},
1486 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1487 {0xaa5555aa, 0xaaaaaaaa},
1488 {0xffffffff, 0x5a5a5a5a},
1489 {0xffffffff, 0x5a5a5a5a},
1490 {0xffffffff, 0x55555555},
1491 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1492 {0x55555555, 0x5a5a5a5a},
1493 {0x55555555, 0xaaaaaaaa},
1494 {0x55555555, 0x6a5a6a5a},
1495 {0x66556655, 0x66556655},
1496 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1497 {0xffffffff, 0x5aaa5aaa},
1498 {0x56555555, 0x5a5a5aaa},
1503 {0xffffffff, 0xffffffff}, /* case-100 */
1504 {0x55555555, 0x55555555},
1505 {0x66555555, 0x66555555},
1506 {0xaaaaaaaa, 0xaaaaaaaa},
1507 {0x5a5a5a5a, 0x5a5a5a5a},
1508 {0xfafafafa, 0xfafafafa}, /* case-105 */
1509 {0x5afa5afa, 0x5afa5afa},
1510 {0x55555555, 0xfafafafa},
1511 {0x66555555, 0xfafafafa},
1512 {0x66555555, 0x5a5a5a5a},
1513 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1514 {0x66555555, 0xaaaaaaaa},
1515 {0xffff55ff, 0xfafafafa},
1516 {0xffff55ff, 0x5afa5afa},
1517 {0xffff55ff, 0xaaaaaaaa},
1518 {0xffff55ff, 0xffff55ff}, /* case-115 */
1519 {0xaaffffaa, 0x5afa5afa},
1520 {0xaaffffaa, 0xaaaaaaaa},
1521 {0xffffffff, 0xfafafafa},
1522 {0xffffffff, 0x5afa5afa},
1523 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1524 {0x55ff55ff, 0x5afa5afa},
1525 {0x55ff55ff, 0xaaaaaaaa},
1526 {0x55ff55ff, 0x55ff55ff}
1531 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1532 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1533 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1534 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1535 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1536 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
1537 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1538 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1539 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1540 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1541 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1542 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1543 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1544 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1545 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1546 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1547 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1548 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1549 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1550 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1551 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1552 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1553 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
1554 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1555 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1556 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1557 { {0x51, 0x08, 0x03, 0x10, 0x50} },
1558 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1563 { {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */
1564 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
1565 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1566 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1567 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1568 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1569 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1570 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1571 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1572 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1573 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1574 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1575 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1576 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1577 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1578 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1579 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1580 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1581 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1582 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1583 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
1584 { {0x51, 0x08, 0x03, 0x10, 0x50} }
1590 static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} };
1598 {0, 0, false, 7}, /* for normal */
1599 {0, 10, false, 7}, /* for WL-CPT */
1600 {1, 0, true, 4},
1607 {0, 0, false, 7}, /* for normal */
1608 {0, 10, false, 7}, /* for WL-CPT */
1609 {1, 0, true, 5},
1616 {0x0005,
1620 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
1621 {0x0086,
1625 RTW_PWR_CMD_WRITE, BIT(0), 0},
1626 {0x0086,
1631 {0x004A,
1635 RTW_PWR_CMD_WRITE, BIT(0), 0},
1636 {0x0005,
1640 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
1641 {0x0023,
1645 RTW_PWR_CMD_WRITE, BIT(4), 0},
1646 {0x0301,
1650 RTW_PWR_CMD_WRITE, 0xFF, 0},
1651 {0xFFFF,
1654 0,
1655 RTW_PWR_CMD_END, 0, 0},
1659 {0x0020,
1663 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1664 {0x0001,
1669 {0x0000,
1673 RTW_PWR_CMD_WRITE, BIT(5), 0},
1674 {0x0005,
1678 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1679 {0x0075,
1683 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1684 {0x0006,
1689 {0x0075,
1693 RTW_PWR_CMD_WRITE, BIT(0), 0},
1694 {0x0006,
1698 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1699 {0x0005,
1703 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0},
1704 {0x0005,
1708 RTW_PWR_CMD_WRITE, BIT(7), 0},
1709 {0x0005,
1713 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1714 {0x0005,
1718 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1719 {0x0005,
1723 RTW_PWR_CMD_POLLING, BIT(0), 0},
1724 {0x0010,
1729 {0x0049,
1734 {0x0063,
1739 {0x0062,
1743 RTW_PWR_CMD_WRITE, BIT(1), 0},
1744 {0x0058,
1748 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1749 {0x005A,
1754 {0x0068,
1759 {0x0069,
1764 {0x001f,
1768 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1769 {0x0077,
1773 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1774 {0x001f,
1778 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
1779 {0x0077,
1783 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
1784 {0xFFFF,
1787 0,
1788 RTW_PWR_CMD_END, 0, 0},
1798 {0x0301,
1802 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
1803 {0x0522,
1807 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
1808 {0x05F8,
1812 RTW_PWR_CMD_POLLING, 0xFF, 0},
1813 {0x05F9,
1817 RTW_PWR_CMD_POLLING, 0xFF, 0},
1818 {0x05FA,
1822 RTW_PWR_CMD_POLLING, 0xFF, 0},
1823 {0x05FB,
1827 RTW_PWR_CMD_POLLING, 0xFF, 0},
1828 {0x0002,
1832 RTW_PWR_CMD_WRITE, BIT(0), 0},
1833 {0x0002,
1837 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
1838 {0x0002,
1842 RTW_PWR_CMD_WRITE, BIT(1), 0},
1843 {0x0100,
1847 RTW_PWR_CMD_WRITE, 0xFF, 0x03},
1848 {0x0101,
1852 RTW_PWR_CMD_WRITE, BIT(1), 0},
1853 {0x0093,
1857 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1858 {0x0553,
1863 {0xFFFF,
1866 0,
1867 RTW_PWR_CMD_END, 0, 0},
1871 {0x0003,
1875 RTW_PWR_CMD_WRITE, BIT(2), 0},
1876 {0x0080,
1880 RTW_PWR_CMD_WRITE, 0xFF, 0},
1881 {0xFFFF,
1884 0,
1885 RTW_PWR_CMD_END, 0, 0},
1889 {0x0002,
1893 RTW_PWR_CMD_WRITE, BIT(0), 0},
1894 {0x0049,
1898 RTW_PWR_CMD_WRITE, BIT(1), 0},
1899 {0x0006,
1903 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1904 {0x0005,
1909 {0x0005,
1913 RTW_PWR_CMD_POLLING, BIT(1), 0},
1914 {0x0010,
1918 RTW_PWR_CMD_WRITE, BIT(6), 0},
1919 {0x0000,
1924 {0x0020,
1928 RTW_PWR_CMD_WRITE, BIT(0), 0},
1929 {0xFFFF,
1932 0,
1933 RTW_PWR_CMD_END, 0, 0},
1937 {0x0007,
1941 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1942 {0x0005,
1947 {0x0005,
1952 {0x0005,
1957 {0x004A,
1961 RTW_PWR_CMD_WRITE, BIT(0), 1},
1962 {0x0023,
1967 {0x0086,
1971 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1972 {0x0086,
1976 RTW_PWR_CMD_POLLING, BIT(1), 0},
1977 {0xFFFF,
1980 0,
1981 RTW_PWR_CMD_END, 0, 0},
1985 {0x001D,
1989 RTW_PWR_CMD_WRITE, BIT(0), 0},
1990 {0x001D,
1994 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1995 {0x001C,
1999 RTW_PWR_CMD_WRITE, 0xFF, 0x0E},
2000 {0xFFFF,
2003 0,
2004 RTW_PWR_CMD_END, 0, 0},
2017 {12, 2, 2, 0, 1},
2018 {12, 2, 2, 0, 1},
2019 {12, 2, 2, 0, 1},
2020 {12, 2, 2, 0, 1},
2021 {12, 2, 2, 0, 1},
2043 {0x0008, 0x4a22,
2047 {0x0009, 0x1000,
2051 {0xFFFF, 0x0000,
2063 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl,
2068 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2073 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2078 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2083 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2088 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2093 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2098 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2103 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2108 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2109 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2113 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2114 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16
2131 {0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2132 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8},
2133 {0, 0, RTW_REG_DOMAIN_NL},
2134 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8},
2135 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8},
2136 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8},
2137 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8},
2138 {0, 0, RTW_REG_DOMAIN_NL},
2139 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2140 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2141 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2142 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2143 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2144 {0, 0, RTW_REG_DOMAIN_NL},
2145 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2146 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2147 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2148 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2149 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2169 .max_power_index = 0x3f,
2170 .csi_buf_pg_num = 0,
2173 .dig_min = 0x20,
2177 .lps_deep_mode_supported = 0,
2178 .sys_func_en = 0xFD,
2187 .rf_sipi_addr = {0x840, 0x844},
2203 .coex_para_ver = 0x2007022f,
2204 .bt_desired_ver = 0x2f,
2226 .bt_afh_span_bw20 = 0x20,
2227 .bt_afh_span_bw40 = 0x30,