28 	[WF_AGG_BASE]		= { { 0x820e2000, 0x820f2000, 0x830e2000 } },
29 	[WF_ARB_BASE]		= { { 0x820e3000, 0x820f3000, 0x830e3000 } },
30 	[WF_TMAC_BASE]		= { { 0x820e4000, 0x820f4000, 0x830e4000 } },
31 	[WF_RMAC_BASE]		= { { 0x820e5000, 0x820f5000, 0x830e5000 } },
32 	[WF_DMA_BASE]		= { { 0x820e7000, 0x820f7000, 0x830e7000 } },
33 	[WF_WTBLOFF_BASE]	= { { 0x820e9000, 0x820f9000, 0x830e9000 } },
34 	[WF_ETBF_BASE]		= { { 0x820ea000, 0x820fa000, 0x830ea000 } },
35 	[WF_LPON_BASE]		= { { 0x820eb000, 0x820fb000, 0x830eb000 } },
36 	[WF_MIB_BASE]		= { { 0x820ed000, 0x820fd000, 0x830ed000 } },
37 	[WF_RATE_BASE]		= { { 0x820ee000, 0x820fe000, 0x830ee000 } },
41 	[MIB_RVSR0]		= 0x720,
42 	[MIB_RVSR1]		= 0x724,
43 	[MIB_BTSCR5]		= 0x788,
44 	[MIB_BTSCR6]		= 0x798,
45 	[MIB_RSCR1]		= 0x7ac,
46 	[MIB_RSCR27]		= 0x954,
47 	[MIB_RSCR28]		= 0x958,
48 	[MIB_RSCR29]		= 0x95c,
49 	[MIB_RSCR30]		= 0x960,
50 	[MIB_RSCR31]		= 0x964,
51 	[MIB_RSCR33]		= 0x96c,
52 	[MIB_RSCR35]		= 0x974,
53 	[MIB_RSCR36]		= 0x978,
54 	[MIB_BSCR0]		= 0x9cc,
55 	[MIB_BSCR1]		= 0x9d0,
56 	[MIB_BSCR2]		= 0x9d4,
57 	[MIB_BSCR3]		= 0x9d8,
58 	[MIB_BSCR4]		= 0x9dc,
59 	[MIB_BSCR5]		= 0x9e0,
60 	[MIB_BSCR6]		= 0x9e4,
61 	[MIB_BSCR7]		= 0x9e8,
62 	[MIB_BSCR17]		= 0xa10,
63 	[MIB_TRDR1]		= 0xa28,
64 	[HIF_REMAP_L1]		= 0x24,
65 	[HIF_REMAP_BASE_L1]	= 0x130000,
66 	[HIF_REMAP_L2]		= 0x1b4,
67 	[HIF_REMAP_BASE_L2]	= 0x1000,
68 	[CBTOP1_PHY_END]	= 0x77ffffff,
69 	[INFRA_MCU_END]		= 0x7c3fffff,
70 	[WTBLON_WDUCR]		= 0x370,
71 	[WTBL_UPDATE]		= 0x380,
72 	[WTBL_ITCR]		= 0x3b0,
73 	[WTBL_ITCR0]		= 0x3b8,
74 	[WTBL_ITCR1]		= 0x3bc,
78 	[MIB_RVSR0]		= 0x760,
79 	[MIB_RVSR1]		= 0x764,
80 	[MIB_BTSCR5]		= 0x7c8,
81 	[MIB_BTSCR6]		= 0x7d8,
82 	[MIB_RSCR1]		= 0x7f0,
83 	[MIB_RSCR27]		= 0x998,
84 	[MIB_RSCR28]		= 0x99c,
85 	[MIB_RSCR29]		= 0x9a0,
86 	[MIB_RSCR30]		= 0x9a4,
87 	[MIB_RSCR31]		= 0x9a8,
88 	[MIB_RSCR33]		= 0x9b0,
89 	[MIB_RSCR35]		= 0x9b8,
90 	[MIB_RSCR36]		= 0x9bc,
91 	[MIB_BSCR0]		= 0xac8,
92 	[MIB_BSCR1]		= 0xacc,
93 	[MIB_BSCR2]		= 0xad0,
94 	[MIB_BSCR3]		= 0xad4,
95 	[MIB_BSCR4]		= 0xad8,
96 	[MIB_BSCR5]		= 0xadc,
97 	[MIB_BSCR6]		= 0xae0,
98 	[MIB_BSCR7]		= 0xae4,
99 	[MIB_BSCR17]		= 0xb0c,
100 	[MIB_TRDR1]		= 0xb24,
101 	[HIF_REMAP_L1]		= 0x8,
102 	[HIF_REMAP_BASE_L1]	= 0x40000,
103 	[HIF_REMAP_L2]		= 0x1b4,
104 	[HIF_REMAP_BASE_L2]	= 0x1000,
105 	[CBTOP1_PHY_END]	= 0x77ffffff,
106 	[INFRA_MCU_END]		= 0x7c3fffff,
107 	[WTBLON_WDUCR]		= 0x370,
108 	[WTBL_UPDATE]		= 0x380,
109 	[WTBL_ITCR]		= 0x3b0,
110 	[WTBL_ITCR0]		= 0x3b8,
111 	[WTBL_ITCR1]		= 0x3bc,
115 	[MIB_RVSR0]		= 0x800,
116 	[MIB_RVSR1]		= 0x804,
117 	[MIB_BTSCR5]		= 0x868,
118 	[MIB_BTSCR6]		= 0x878,
119 	[MIB_RSCR1]		= 0x890,
120 	[MIB_RSCR27]		= 0xa38,
121 	[MIB_RSCR28]		= 0xa3c,
122 	[MIB_RSCR29]		= 0xa40,
123 	[MIB_RSCR30]		= 0xa44,
124 	[MIB_RSCR31]		= 0xa48,
125 	[MIB_RSCR33]		= 0xa50,
126 	[MIB_RSCR35]		= 0xa58,
127 	[MIB_RSCR36]		= 0xa5c,
128 	[MIB_BSCR0]		= 0xbb8,
129 	[MIB_BSCR1]		= 0xbbc,
130 	[MIB_BSCR2]		= 0xbc0,
131 	[MIB_BSCR3]		= 0xbc4,
132 	[MIB_BSCR4]		= 0xbc8,
133 	[MIB_BSCR5]		= 0xbcc,
134 	[MIB_BSCR6]		= 0xbd0,
135 	[MIB_BSCR7]		= 0xbd4,
136 	[MIB_BSCR17]		= 0xbfc,
137 	[MIB_TRDR1]		= 0xc14,
138 	[HIF_REMAP_L1]		= 0x8,
139 	[HIF_REMAP_BASE_L1]	= 0x40000,
140 	[HIF_REMAP_L2]		= 0x1b8,
141 	[HIF_REMAP_BASE_L2]	= 0x110000,
142 	[CBTOP1_PHY_END]	= 0x7fffffff,
143 	[INFRA_MCU_END]		= 0x7cffffff,
144 	[WTBLON_WDUCR]		= 0x400,
145 	[WTBL_UPDATE]		= 0x410,
146 	[WTBL_ITCR]		= 0x440,
147 	[WTBL_ITCR0]		= 0x448,
148 	[WTBL_ITCR1]		= 0x44c,
152 	{ 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
153 	{ 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
154 	{ 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */
155 	{ 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */
156 	{ 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
157 	{ 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
158 	{ 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
159 	{ 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
160 	{ 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
161 	{ 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */
162 	{ 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
163 	{ 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
164 	{ 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
165 	{ 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
166 	{ 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
167 	{ 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
168 	{ 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
169 	{ 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
170 	{ 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
171 	{ 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
172 	{ 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
173 	{ 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
174 	{ 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
175 	{ 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
176 	{ 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
177 	{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
178 	{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
179 	{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
180 	{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
181 	{ 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
182 	{ 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
183 	{ 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
184 	{ 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
185 	{ 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
186 	{ 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
187 	{ 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
188 	{ 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
189 	{ 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
190 	{ 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
191 	{ 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
192 	{ 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
193 	{ 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
194 	{ 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
195 	{ 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
196 	{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
197 	{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
198 	{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */
199 	{ 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
200 	{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
201 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
205 	{0x54000000, 0x02000, 0x1000}, /* WFDMA_0 (PCIE0 MCU DMA0) */
206 	{0x55000000, 0x03000, 0x1000}, /* WFDMA_1 (PCIE0 MCU DMA1) */
207 	{0x56000000, 0x04000, 0x1000}, /* WFDMA_2 (Reserved) */
208 	{0x57000000, 0x05000, 0x1000}, /* WFDMA_3 (MCU wrap CR) */
209 	{0x58000000, 0x06000, 0x1000}, /* WFDMA_4 (PCIE1 MCU DMA0 (MEM_DMA)) */
210 	{0x59000000, 0x07000, 0x1000}, /* WFDMA_5 (PCIE1 MCU DMA1) */
211 	{0x820c0000, 0x08000, 0x4000}, /* WF_UMAC_TOP (PLE) */
212 	{0x820c8000, 0x0c000, 0x2000}, /* WF_UMAC_TOP (PSE) */
213 	{0x820cc000, 0x0e000, 0x2000}, /* WF_UMAC_TOP (PP) */
214 	{0x820e0000, 0x20000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_CFG) */
215 	{0x820e1000, 0x20400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_TRB) */
216 	{0x820e2000, 0x20800, 0x0400}, /* WF_LMAC_TOP BN0 (WF_AGG) */
217 	{0x820e3000, 0x20c00, 0x0400}, /* WF_LMAC_TOP BN0 (WF_ARB) */
218 	{0x820e4000, 0x21000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_TMAC) */
219 	{0x820e5000, 0x21400, 0x0800}, /* WF_LMAC_TOP BN0 (WF_RMAC) */
220 	{0x820ce000, 0x21c00, 0x0200}, /* WF_LMAC_TOP (WF_SEC) */
221 	{0x820e7000, 0x21e00, 0x0200}, /* WF_LMAC_TOP BN0 (WF_DMA) */
222 	{0x820cf000, 0x22000, 0x1000}, /* WF_LMAC_TOP (WF_PF) */
223 	{0x820e9000, 0x23400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
224 	{0x820ea000, 0x24000, 0x0200}, /* WF_LMAC_TOP BN0 (WF_ETBF) */
225 	{0x820eb000, 0x24200, 0x0400}, /* WF_LMAC_TOP BN0 (WF_LPON) */
226 	{0x820ec000, 0x24600, 0x0200}, /* WF_LMAC_TOP BN0 (WF_INT) */
227 	{0x820ed000, 0x24800, 0x0800}, /* WF_LMAC_TOP BN0 (WF_MIB) */
228 	{0x820ca000, 0x26000, 0x2000}, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
229 	{0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
230 	{0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */
231 	{0x820f0000, 0xa0000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_CFG) */
232 	{0x820f1000, 0xa0600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_TRB) */
233 	{0x820f2000, 0xa0800, 0x0400}, /* WF_LMAC_TOP BN1 (WF_AGG) */
234 	{0x820f3000, 0xa0c00, 0x0400}, /* WF_LMAC_TOP BN1 (WF_ARB) */
235 	{0x820f4000, 0xa1000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_TMAC) */
236 	{0x820f5000, 0xa1400, 0x0800}, /* WF_LMAC_TOP BN1 (WF_RMAC) */
237 	{0x820f7000, 0xa1e00, 0x0200}, /* WF_LMAC_TOP BN1 (WF_DMA) */
238 	{0x820f9000, 0xa3400, 0x0200}, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
239 	{0x820fa000, 0xa4000, 0x0200}, /* WF_LMAC_TOP BN1 (WF_ETBF) */
240 	{0x820fb000, 0xa4200, 0x0400}, /* WF_LMAC_TOP BN1 (WF_LPON) */
241 	{0x820fc000, 0xa4600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_INT) */
242 	{0x820fd000, 0xa4800, 0x0800}, /* WF_LMAC_TOP BN1 (WF_MIB) */
243 	{0x820cc000, 0xa5000, 0x2000}, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
244 	{0x820c4000, 0xa8000, 0x4000}, /* WF_LMAC_TOP (WF_UWTBL) */
245 	{0x81030000, 0xae000, 0x100}, /* WFSYS_AON part 1 */
246 	{0x81031000, 0xae100, 0x100}, /* WFSYS_AON part 2 */
247 	{0x81032000, 0xae200, 0x100}, /* WFSYS_AON part 3 */
248 	{0x81033000, 0xae300, 0x100}, /* WFSYS_AON part 4 */
249 	{0x81034000, 0xae400, 0x100}, /* WFSYS_AON part 5 */
250 	{0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */
251 	{0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */
252 	{0x81040000, 0x120000, 0x1000}, /* WF_MCU_CFG_ON */
253 	{0x81050000, 0x121000, 0x1000}, /* WF_MCU_EINT */
254 	{0x81060000, 0x122000, 0x1000}, /* WF_MCU_GPT */
255 	{0x81070000, 0x123000, 0x1000}, /* WF_MCU_WDT */
256 	{0x80010000, 0x124000, 0x1000}, /* WF_AXIDMA */
257 	{0x7c020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma for from CODA flow use */
258 	{0x7c060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top for from CODA flow use */
259 	{0x20020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma */
260 	{0x20060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top */
261 	{0x7c000000, 0xf0000, 0x10000}, /* CONN_INFRA */
262 	{0x70020000, 0x1f0000, 0x9000}, /* PCIE remapping (AP2CONN) */
263 	{0x0, 0x0, 0x0}, /* imply end of search */
328 	if (addr < 0x100000)  in __mt7996_reg_addr()
331 	for (i = 0; i < dev->reg.map_size; i++) {  in __mt7996_reg_addr()
344 	return 0;  in __mt7996_reg_addr()
477 	u32 hif1_ofs = 0;  in mt7996_mmio_wed_init()
480 		return 0;  in mt7996_mmio_wed_init()
484 	hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7996_mmio_wed_init()
493 				      pci_resource_start(pci_dev, 0),  in mt7996_mmio_wed_init()
494 				      pci_resource_len(pci_dev, 0));  in mt7996_mmio_wed_init()
498 	wed->wlan.phy_base = pci_resource_start(pci_dev, 0);  in mt7996_mmio_wed_init()
506 					     MT_TXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
510 						 MT_RXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
515 						 MT_RXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
526 		wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND2) - 1;  in mt7996_mmio_wed_init()
531 		wed->wlan.wpdma_tx = wed->wlan.phy_base + MT_TXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
540 		wed->wlan.wpdma_rx_rro[0] = wed->wlan.phy_base +  in mt7996_mmio_wed_init()
554 		wed->wlan.rx_tbit[0] = ffs(MT_INT_RX_DONE_BAND0) - 1;  in mt7996_mmio_wed_init()
557 		wed->wlan.rro_rx_tbit[0] = ffs(MT_INT_RX_DONE_RRO_BAND0) - 1;  in mt7996_mmio_wed_init()
560 		wed->wlan.rx_pg_tbit[0] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND0) - 1;  in mt7996_mmio_wed_init()
564 		wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND0) - 1;  in mt7996_mmio_wed_init()
567 			wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
572 			wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
595 		return 0;  in mt7996_mmio_wed_init()
602 	return 0;  in mt7996_mmio_wed_init()
651 	mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff);  in mt7996_mmio_init()
655 	return 0;  in mt7996_mmio_init()
700 	u32 i, intr, mask, intr1 = 0;  in mt7996_irq_tasklet()
703 		mtk_wed_device_irq_set_mask(wed_hif2, 0);  in mt7996_irq_tasklet()
711 		mtk_wed_device_irq_set_mask(wed, 0);  in mt7996_irq_tasklet()
715 		mt76_wr(dev, MT_INT_MASK_CSR, 0);  in mt7996_irq_tasklet()
717 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);  in mt7996_irq_tasklet()
740 	for (i = 0; i < __MT_RXQ_MAX; i++) {  in mt7996_irq_tasklet()
761 		mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed, 0);  in mt7996_irq_handler()
763 		mt76_wr(dev, MT_INT_MASK_CSR, 0);  in mt7996_irq_handler()
767 			mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed_hif2, 0);  in mt7996_irq_handler()
769 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);  in mt7996_irq_handler()
820 	mt76_wr(dev, MT_INT_MASK_CSR, 0);  in mt7996_mmio_probe()