Lines Matching +full:0 +full:x800c0000
6 #define MT_HW_REV 0x1000
7 #define MT_HW_CHIPID 0x1008
8 #define MT_TOP_MISC2 0x1134
10 #define MT_MCU_BASE 0x2000
13 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
17 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
21 #define MT_HIF_BASE 0x4000
24 #define MT_INT_SOURCE_CSR MT_HIF(0x200)
25 #define MT_INT_MASK_CSR MT_HIF(0x204)
26 #define MT_DELAY_INT_CFG MT_HIF(0x210)
29 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
39 #define MT_WPDMA_GLO_CFG MT_HIF(0x208)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
53 #define MT_WPDMA_RST_IDX MT_HIF(0x20c)
55 #define MT_WPDMA_DEBUG MT_HIF(0x244)
56 #define MT_WPDMA_DEBUG_VALUE GENMASK(17, 0)
60 #define MT_TX_RING_BASE MT_HIF(0x300)
61 #define MT_RX_RING_BASE MT_HIF(0x400)
63 #define MT_TXTIME_THRESH_BASE MT_HIF(0x500)
66 #define MT_PAGE_COUNT_BASE MT_HIF(0x540)
69 #define MT_SCH_1 MT_HIF(0x588)
70 #define MT_SCH_2 MT_HIF(0x58c)
71 #define MT_SCH_3 MT_HIF(0x590)
73 #define MT_SCH_4 MT_HIF(0x594)
74 #define MT_SCH_4_FORCE_QID GENMASK(4, 0)
78 #define MT_GROUP_THRESH_BASE MT_HIF(0x598)
81 #define MT_QUEUE_PRIORITY_1 MT_HIF(0x580)
82 #define MT_QUEUE_PRIORITY_2 MT_HIF(0x584)
84 #define MT_BMAP_0 MT_HIF(0x5b0)
85 #define MT_BMAP_1 MT_HIF(0x5b4)
86 #define MT_BMAP_2 MT_HIF(0x5b8)
88 #define MT_HIGH_PRIORITY_1 MT_HIF(0x5bc)
89 #define MT_HIGH_PRIORITY_2 MT_HIF(0x5c0)
91 #define MT_PRIORITY_MASK MT_HIF(0x5c4)
93 #define MT_RSV_MAX_THRESH MT_HIF(0x5c8)
95 #define MT_PSE_BASE 0x8000
98 #define MT_MCU_DEBUG_RESET MT_PSE(0x16c)
99 #define MT_MCU_DEBUG_RESET_PSE BIT(0)
103 #define MT_PSE_FC_P0 MT_PSE(0x120)
104 #define MT_PSE_FC_P0_MIN_RESERVE GENMASK(11, 0)
107 #define MT_PSE_FRP MT_PSE(0x138)
108 #define MT_PSE_FRP_P0 GENMASK(2, 0)
114 #define MT_FC_RSV_COUNT_0 MT_PSE(0x13c)
115 #define MT_FC_RSV_COUNT_0_P0 GENMASK(11, 0)
118 #define MT_FC_SP2_Q0Q1 MT_PSE(0x14c)
119 #define MT_FC_SP2_Q0Q1_SRC_COUNT_Q0 GENMASK(11, 0)
122 #define MT_PSE_FW_SHARED MT_PSE(0x17c)
124 #define MT_PSE_RTA MT_PSE(0x194)
125 #define MT_PSE_RTA_QUEUE_ID GENMASK(4, 0)
132 #define MT_WF_PHY_BASE 0x10000
133 #define MT_WF_PHY_OFFSET 0x1000
136 #define MT_AGC_BASE MT_WF_PHY(0x500)
139 #define MT_AGC1_BASE MT_WF_PHY(0x1500)
143 #define MT_AGC_41_RSSI_1 GENMASK(7, 0)
145 #define MT_RXTD_BASE MT_WF_PHY(0x600)
148 #define MT_RXTD_6_ACI_TH GENMASK(4, 0)
151 #define MT_RXTD_8_LOWER_SIGNAL GENMASK(5, 0)
153 #define MT_RXTD_13_ACI_TH_EN BIT(0)
155 #define MT_WF_PHY_CR_TSSI_BASE MT_WF_PHY(0xd00)
160 #define MT_PHYCTRL_BASE MT_WF_PHY(0x4100)
168 #define MT_PHYCTRL_STAT_PD_CCK GENMASK(15, 0)
172 #define MT_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0)
174 #define MT_WF_AGG_BASE 0x21200
177 #define MT_AGG_ARCR MT_WF_AGG(0x010)
178 #define MT_AGG_ARCR_INIT_RATE1 BIT(0)
187 #define MT_AGG_ARUCR MT_WF_AGG(0x014)
188 #define MT_AGG_ARDCR MT_WF_AGG(0x018)
194 #define MT_AGG_LIMIT MT_WF_AGG(0x040)
195 #define MT_AGG_LIMIT_1 MT_WF_AGG(0x044)
198 #define MT_AGG_BA_SIZE_LIMIT_0 MT_WF_AGG(0x048)
199 #define MT_AGG_BA_SIZE_LIMIT_1 MT_WF_AGG(0x04c)
202 #define MT_AGG_PCR MT_WF_AGG(0x050)
211 #define MT_AGG_PCR_RTS MT_WF_AGG(0x054)
212 #define MT_AGG_PCR_RTS_THR GENMASK(19, 0)
215 #define MT_AGG_ASRCR MT_WF_AGG(0x060)
216 #define MT_AGG_ASRCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(5, 0))
218 #define MT_AGG_CONTROL MT_WF_AGG(0x070)
219 #define MT_AGG_CONTROL_NO_BA_RULE BIT(0)
226 #define MT_AGG_TMP MT_WF_AGG(0x0d8)
228 #define MT_AGG_BWCR MT_WF_AGG(0x0ec)
231 #define MT_AGG_RETRY_CONTROL MT_WF_AGG(0x0f4)
235 #define MT_WF_DMA_BASE 0x21c00
238 #define MT_DMA_DCR0 MT_WF_DMA(0x000)
239 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 0)
243 #define MT_DMA_DCR1 MT_WF_DMA(0x004)
245 #define MT_DMA_FQCR0 MT_WF_DMA(0x008)
246 #define MT_DMA_FQCR0_TARGET_WCID GENMASK(7, 0)
255 #define MT_DMA_RCFR0 MT_WF_DMA(0x070)
256 #define MT_DMA_VCFR0 MT_WF_DMA(0x07c)
258 #define MT_DMA_TCFR0 MT_WF_DMA(0x080)
259 #define MT_DMA_TCFR1 MT_WF_DMA(0x084)
263 #define MT_DMA_TCFR_TXS_BIT_MAP GENMASK(6, 0)
265 #define MT_DMA_TMCFR0 MT_WF_DMA(0x088)
267 #define MT_WF_ARB_BASE 0x21400
270 #define MT_WMM_AIFSN MT_WF_ARB(0x020)
271 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
274 #define MT_WMM_CWMAX_BASE MT_WF_ARB(0x028)
277 #define MT_WMM_CWMAX_MASK GENMASK(15, 0)
279 #define MT_WMM_CWMIN MT_WF_ARB(0x040)
280 #define MT_WMM_CWMIN_MASK GENMASK(7, 0)
283 #define MT_WF_ARB_RQCR MT_WF_ARB(0x070)
284 #define MT_WF_ARB_RQCR_RX_START BIT(0)
289 #define MT_ARB_SCR MT_WF_ARB(0x080)
290 #define MT_ARB_SCR_BCNQ_OPMODE_MASK GENMASK(1, 0)
300 MT_BCNQ_OPMODE_STA = 0,
305 #define MT_WF_ARB_TX_START_0 MT_WF_ARB(0x100)
306 #define MT_WF_ARB_TX_START_1 MT_WF_ARB(0x104)
307 #define MT_WF_ARB_TX_FLUSH_0 MT_WF_ARB(0x108)
308 #define MT_WF_ARB_TX_FLUSH_1 MT_WF_ARB(0x10c)
309 #define MT_WF_ARB_TX_STOP_0 MT_WF_ARB(0x110)
310 #define MT_WF_ARB_TX_STOP_1 MT_WF_ARB(0x114)
312 #define MT_WF_ARB_TX_FLUSH_AC0 BIT(0)
319 #define MT_WF_ARB_BCN_START MT_WF_ARB(0x118)
320 #define MT_WF_ARB_BCN_START_BSSn(n) BIT(0 + (n))
327 #define MT_WF_ARB_BCN_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
329 #define MT_WF_ARB_BCN_FLUSH MT_WF_ARB(0x11c)
330 #define MT_WF_ARB_BCN_FLUSH_BSSn(n) BIT(0 + (n))
331 #define MT_WF_ARB_BCN_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
333 #define MT_WF_ARB_CAB_START MT_WF_ARB(0x120)
334 #define MT_WF_ARB_CAB_START_BSSn(n) BIT(0 + (n))
335 #define MT_WF_ARB_CAB_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
337 #define MT_WF_ARB_CAB_FLUSH MT_WF_ARB(0x124)
338 #define MT_WF_ARB_CAB_FLUSH_BSSn(n) BIT(0 + (n))
339 #define MT_WF_ARB_CAB_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0)
341 #define MT_WF_ARB_CAB_COUNT(n) MT_WF_ARB(0x128 + (n) * 4)
343 #define MT_WF_ARB_CAB_COUNT_MASK GENMASK(3, 0)
345 ((n) > 4 ? 1 : 0)))
348 (n) ? (n) + 3 : 0)) * 4)
350 #define MT_TX_ABORT MT_WF_ARB(0x134)
351 #define MT_TX_ABORT_EN BIT(0)
354 #define MT_WF_TMAC_BASE 0x21600
357 #define MT_TMAC_TCR MT_WF_TMAC(0x000)
377 #define MT_WMM_TXOP_BASE MT_WF_TMAC(0x010)
379 ((((_n) / 2) ^ 0x1) << 2))
381 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
383 #define MT_TIMEOUT_CCK MT_WF_TMAC(0x090)
384 #define MT_TIMEOUT_OFDM MT_WF_TMAC(0x094)
385 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
388 #define MT_TXREQ MT_WF_TMAC(0x09c)
391 #define MT_RXREQ MT_WF_TMAC(0x0a0)
392 #define MT_RXREQ_DELAY GENMASK(8, 0)
394 #define MT_IFS MT_WF_TMAC(0x0a4)
395 #define MT_IFS_EIFS GENMASK(8, 0)
400 #define MT_TMAC_PCR MT_WF_TMAC(0x0b4)
401 #define MT_TMAC_PCR_RATE GENMASK(8, 0)
409 #define MT_WF_RMAC_BASE 0x21800
412 #define MT_WF_RFCR MT_WF_RMAC(0x000)
413 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
435 #define MT_BSSID0(idx) MT_WF_RMAC(0x004 + (idx) * 8)
436 #define MT_BSSID1(idx) MT_WF_RMAC(0x008 + (idx) * 8)
439 #define MT_MAC_ADDR0(idx) MT_WF_RMAC(0x024 + (idx) * 8)
440 #define MT_MAC_ADDR1(idx) MT_WF_RMAC(0x028 + (idx) * 8)
441 #define MT_MAC_ADDR1_ADDR GENMASK(15, 0)
444 #define MT_BA_CONTROL_0 MT_WF_RMAC(0x068)
445 #define MT_BA_CONTROL_1 MT_WF_RMAC(0x06c)
446 #define MT_BA_CONTROL_1_ADDR GENMASK(15, 0)
452 #define MT_WF_RMACDR MT_WF_RMAC(0x078)
453 #define MT_WF_RMACDR_TSF_PROBERSP_DIS BIT(0)
459 #define MT_WF_RMAC_RMCR MT_WF_RMAC(0x080)
464 #define MT_WF_RMAC_CH_FREQ MT_WF_RMAC(0x090)
465 #define MT_WF_RMAC_MAXMINLEN MT_WF_RMAC(0x098)
466 #define MT_WF_RFCR1 MT_WF_RMAC(0x0a4)
467 #define MT_WF_RMAC_TMR_PA MT_WF_RMAC(0x0e0)
469 #define MT_WF_SEC_BASE 0x21a00
472 #define MT_SEC_SCR MT_WF_SEC(0x004)
473 #define MT_SEC_SCR_MASK_ORDER GENMASK(1, 0)
475 #define MT_WTBL_OFF_BASE 0x23000
478 #define MT_WTBL_UPDATE MT_WTBL_OFF(0x000)
479 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0)
487 #define MT_WTBL_RMVTCR MT_WTBL_OFF(0x008)
490 #define MT_LPON_BASE 0x24000
493 #define MT_LPON_T0CR MT_LPON(0x010)
494 #define MT_LPON_T0CR_MODE GENMASK(1, 0)
496 #define MT_LPON_UTTR0 MT_LPON(0x018)
497 #define MT_LPON_UTTR1 MT_LPON(0x01c)
499 #define MT_LPON_BTEIR MT_LPON(0x020)
502 #define MT_PRE_TBTT MT_LPON(0x030)
503 #define MT_PRE_TBTT_MASK GENMASK(7, 0)
506 #define MT_TBTT MT_LPON(0x034)
507 #define MT_TBTT_PERIOD GENMASK(15, 0)
513 #define MT_TBTT_TIMER_CFG MT_LPON(0x05c)
515 #define MT_LPON_SBTOR(n) MT_LPON(0x0a0)
517 #define MT_LPON_SBTOR_TIME_OFFSET GENMASK(19, 0)
519 #define MT_INT_WAKEUP_BASE 0x24400
522 #define MT_HW_INT_STATUS(n) MT_INT_WAKEUP(0x3c + (n) * 8)
523 #define MT_HW_INT_MASK(n) MT_INT_WAKEUP(0x40 + (n) * 8)
528 #define MT_WTBL1_BASE 0x28000
530 #define MT_WTBL_ON_BASE (MT_WTBL1_BASE + 0x2000)
533 #define MT_WTBL_RIUCR0 MT_WTBL_ON(0x200)
535 #define MT_WTBL_RIUCR1 MT_WTBL_ON(0x204)
536 #define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0)
540 #define MT_WTBL_RIUCR2 MT_WTBL_ON(0x208)
541 #define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0)
546 #define MT_WTBL_RIUCR3 MT_WTBL_ON(0x20c)
547 #define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0)
551 #define MT_MIB_BASE 0x2c000
554 #define MT_MIB_CTL MT_MIB(0x00)
560 #define MT_MIB_STAT(_n) MT_MIB(0x08 + (_n) * 4)
563 #define MT_MIB_STAT_CCA_MASK GENMASK(23, 0)
566 #define MT_MIB_STAT_PSCCA_MASK GENMASK(23, 0)
568 #define MT_TX_AGG_CNT(n) MT_MIB(0xa8 + ((n) << 2))
571 #define MT_MIB_STAT_ED_MASK GENMASK(23, 0)
573 #define MT_PCIE_REMAP_BASE_1 0x40000
574 #define MT_PCIE_REMAP_BASE_2 0x80000
581 #define MT_LED_BASE_PHYS 0x80024000
584 #define MT_LED_CTRL MT_LED_PHYS(0x00)
586 #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n)))
593 #define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x10 + ((_n) * 8))
594 #define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x14 + ((_n) * 8))
597 #define MT_LED_STATUS_DURATION GENMASK(15, 0)
599 #define MT_CLIENT_BASE_PHYS_ADDR 0x800c0000
601 #define MT_CLIENT_TMAC_INFO_TEMPLATE 0x040
603 #define MT_CLIENT_STATUS 0x06c
605 #define MT_CLIENT_RESET_TX 0x070
611 #define MT_EFUSE_BASE 0x81070000
613 #define MT_EFUSE_BASE_CTRL 0x000
616 #define MT_EFUSE_CTRL 0x008
617 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
626 #define MT_EFUSE_WDATA(_i) (0x010 + ((_i) * 4))
627 #define MT_EFUSE_RDATA(_i) (0x030 + ((_i) * 4))
629 #define MT_CLIENT_RXINF 0x068
630 #define MT_CLIENT_RXINF_RXSH_GROUPS GENMASK(2, 0)
632 #define MT_PSE_BASE_PHYS_ADDR 0xa0000000
634 #define MT_PSE_WTBL_2_PHYS_ADDR 0xa5000000
644 #define MT_WTBL1_W0_ADDR_HI GENMASK(15, 0)
656 #define MT_WTBL1_W1_ADDR_LO GENMASK(31, 0)
658 #define MT_WTBL1_W2_MPDU_DENSITY GENMASK(2, 0)
684 #define MT_WTBL1_W3_WTBL2_FRAME_ID GENMASK(10, 0)
693 #define MT_WTBL1_W4_WTBL3_FRAME_ID GENMASK(10, 0)
698 #define MT_WTBL2_W0_PN_LO GENMASK(31, 0)
700 #define MT_WTBL2_W1_PN_HI GENMASK(15, 0)
703 #define MT_WTBL2_W2_TID0_SN GENMASK(11, 0)
707 #define MT_WTBL2_W3_TID2_SN_HI GENMASK(3, 0)
712 #define MT_WTBL2_W4_TID5_SN_HI GENMASK(7, 0)
716 #define MT_WTBL2_W5_TX_COUNT_RATE1 GENMASK(15, 0)
719 #define MT_WTBL2_W6_TX_COUNT_RATE2 GENMASK(7, 0)
724 #define MT_WTBL2_W7_TX_COUNT_CUR_BW GENMASK(15, 0)
727 #define MT_WTBL2_W8_TX_COUNT_OTHER_BW GENMASK(15, 0)
730 #define MT_WTBL2_W9_POWER_OFFSET GENMASK(4, 0)
744 #define MT_WTBL2_W10_RATE1 GENMASK(11, 0)
748 #define MT_WTBL2_W11_RATE3_HI GENMASK(3, 0)
753 #define MT_WTBL2_W12_RATE6_HI GENMASK(7, 0)
757 #define MT_WTBL2_W13_AVG_RCPI0 GENMASK(7, 0)
761 #define MT_WTBL2_W14_CC_NOISE_1S GENMASK(6, 0)
768 #define MT_WTBL2_W15_BA_WIN_SIZE GENMASK(2, 0)
772 #define MT_WTBL1_OR (MT_WTBL1_BASE + 0x2300)