Lines Matching +full:transfer +full:- +full:function

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3  * Copyright (C) 2018, 2020-2024 Intel Corporation
8 #include "iwl-context-info.h"
18 /* Set bit for enabling automatic function boot */
20 /* Set bit for initiating function boot */
24  * enum iwl_prph_scratch_mtr_format - tfd size configuration
38  * enum iwl_prph_scratch_flags - PRPH scratch control flags
48  * @IWL_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for
80  * struct iwl_prph_scratch_version - version structure
94  * struct iwl_prph_scratch_control - control structure
104  * struct iwl_prph_scratch_pnvm_cfg - PNVM scratch
124  * struct iwl_prph_scratch_hwm_cfg - hwm config
136  * struct iwl_prph_scratch_rbd_cfg - RBDs configuration
146  * struct iwl_prph_scratch_uefi_cfg - prph scratch reduce power table
157  * struct iwl_prph_scratch_step_cfg - prph scratch step configuration
171  * struct iwl_prph_scratch_ctrl_cfg - prph scratch ctrl and config
190  * struct iwl_prph_scratch - peripheral scratch mapping
206  * struct iwl_prph_info - peripheral information
220  * struct iwl_context_info_gen3 - device INIT configuration
223  * @config: context in which the peripheral would execute - a subset of
228  * @tr_tail_idx_arr_base_addr: the transfer ring tail index array
232  * @tr_head_idx_arr_base_addr: the transfer ring head index array
235  * @tr_idx_arr_size: number of entries in the transfer ring index array
236  * @mtr_base_addr: the message transfer ring start address
238  * @mtr_size: number of entries which the message transfer ring can hold
241  *	transfer ring
245  *	completing a transfer descriptor in the message transfer ring
248  * @mtr_opt_header_size: the size of the optional header in the transfer
249  *	descriptor associated with the message transfer ring in DWs
250  * @mtr_opt_footer_size: the size of the optional footer in the transfer
251  *	descriptor associated with the message transfer ring in DWs