Lines Matching +full:0 +full:x00a08000
33 #define RADIO_REG_MAX_READ 0x2ad
48 for (i = 0; i < RADIO_REG_MAX_READ; i++) {
76 /* No need to try to read the data if the length is 0 */
77 if (fifo_len == 0)
102 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1);
104 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1);
107 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0);
111 for (i = 0; i < fifo_len; i++)
131 /* No need to try to read the data if the length is 0 */
132 if (fifo_len == 0)
164 for (i = 0; i < fifo_len / sizeof(u32); i++)
189 cfg->lmac[0].rxfifo1_size, 0, 0);
220 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
224 cfg->lmac[0].txfifo_size[i], 0, i);
229 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries;
247 for (i = 0;
254 /* No need to try to read the data if the length is 0 */
255 if (fifo_len == 0)
297 for (j = 0; j < fifo_len; j++)
313 { .start = 0x00a00000, .end = 0x00a00000 },
314 { .start = 0x00a0000c, .end = 0x00a00024 },
315 { .start = 0x00a0002c, .end = 0x00a0003c },
316 { .start = 0x00a00410, .end = 0x00a00418 },
317 { .start = 0x00a00420, .end = 0x00a00420 },
318 { .start = 0x00a00428, .end = 0x00a00428 },
319 { .start = 0x00a00430, .end = 0x00a0043c },
320 { .start = 0x00a00444, .end = 0x00a00444 },
321 { .start = 0x00a004c0, .end = 0x00a004cc },
322 { .start = 0x00a004d8, .end = 0x00a004d8 },
323 { .start = 0x00a004e0, .end = 0x00a004f0 },
324 { .start = 0x00a00840, .end = 0x00a00840 },
325 { .start = 0x00a00850, .end = 0x00a00858 },
326 { .start = 0x00a01004, .end = 0x00a01008 },
327 { .start = 0x00a01010, .end = 0x00a01010 },
328 { .start = 0x00a01018, .end = 0x00a01018 },
329 { .start = 0x00a01024, .end = 0x00a01024 },
330 { .start = 0x00a0102c, .end = 0x00a01034 },
331 { .start = 0x00a0103c, .end = 0x00a01040 },
332 { .start = 0x00a01048, .end = 0x00a01094 },
333 { .start = 0x00a01c00, .end = 0x00a01c20 },
334 { .start = 0x00a01c58, .end = 0x00a01c58 },
335 { .start = 0x00a01c7c, .end = 0x00a01c7c },
336 { .start = 0x00a01c28, .end = 0x00a01c54 },
337 { .start = 0x00a01c5c, .end = 0x00a01c5c },
338 { .start = 0x00a01c60, .end = 0x00a01cdc },
339 { .start = 0x00a01ce0, .end = 0x00a01d0c },
340 { .start = 0x00a01d18, .end = 0x00a01d20 },
341 { .start = 0x00a01d2c, .end = 0x00a01d30 },
342 { .start = 0x00a01d40, .end = 0x00a01d5c },
343 { .start = 0x00a01d80, .end = 0x00a01d80 },
344 { .start = 0x00a01d98, .end = 0x00a01d9c },
345 { .start = 0x00a01da8, .end = 0x00a01da8 },
346 { .start = 0x00a01db8, .end = 0x00a01df4 },
347 { .start = 0x00a01dc0, .end = 0x00a01dfc },
348 { .start = 0x00a01e00, .end = 0x00a01e2c },
349 { .start = 0x00a01e40, .end = 0x00a01e60 },
350 { .start = 0x00a01e68, .end = 0x00a01e6c },
351 { .start = 0x00a01e74, .end = 0x00a01e74 },
352 { .start = 0x00a01e84, .end = 0x00a01e90 },
353 { .start = 0x00a01e9c, .end = 0x00a01ec4 },
354 { .start = 0x00a01ed0, .end = 0x00a01ee0 },
355 { .start = 0x00a01f00, .end = 0x00a01f1c },
356 { .start = 0x00a01f44, .end = 0x00a01ffc },
357 { .start = 0x00a02000, .end = 0x00a02048 },
358 { .start = 0x00a02068, .end = 0x00a020f0 },
359 { .start = 0x00a02100, .end = 0x00a02118 },
360 { .start = 0x00a02140, .end = 0x00a0214c },
361 { .start = 0x00a02168, .end = 0x00a0218c },
362 { .start = 0x00a021c0, .end = 0x00a021c0 },
363 { .start = 0x00a02400, .end = 0x00a02410 },
364 { .start = 0x00a02418, .end = 0x00a02420 },
365 { .start = 0x00a02428, .end = 0x00a0242c },
366 { .start = 0x00a02434, .end = 0x00a02434 },
367 { .start = 0x00a02440, .end = 0x00a02460 },
368 { .start = 0x00a02468, .end = 0x00a024b0 },
369 { .start = 0x00a024c8, .end = 0x00a024cc },
370 { .start = 0x00a02500, .end = 0x00a02504 },
371 { .start = 0x00a0250c, .end = 0x00a02510 },
372 { .start = 0x00a02540, .end = 0x00a02554 },
373 { .start = 0x00a02580, .end = 0x00a025f4 },
374 { .start = 0x00a02600, .end = 0x00a0260c },
375 { .start = 0x00a02648, .end = 0x00a02650 },
376 { .start = 0x00a02680, .end = 0x00a02680 },
377 { .start = 0x00a026c0, .end = 0x00a026d0 },
378 { .start = 0x00a02700, .end = 0x00a0270c },
379 { .start = 0x00a02804, .end = 0x00a02804 },
380 { .start = 0x00a02818, .end = 0x00a0281c },
381 { .start = 0x00a02c00, .end = 0x00a02db4 },
382 { .start = 0x00a02df4, .end = 0x00a02fb0 },
383 { .start = 0x00a03000, .end = 0x00a03014 },
384 { .start = 0x00a0301c, .end = 0x00a0302c },
385 { .start = 0x00a03034, .end = 0x00a03038 },
386 { .start = 0x00a03040, .end = 0x00a03048 },
387 { .start = 0x00a03060, .end = 0x00a03068 },
388 { .start = 0x00a03070, .end = 0x00a03074 },
389 { .start = 0x00a0307c, .end = 0x00a0307c },
390 { .start = 0x00a03080, .end = 0x00a03084 },
391 { .start = 0x00a0308c, .end = 0x00a03090 },
392 { .start = 0x00a03098, .end = 0x00a03098 },
393 { .start = 0x00a030a0, .end = 0x00a030a0 },
394 { .start = 0x00a030a8, .end = 0x00a030b4 },
395 { .start = 0x00a030bc, .end = 0x00a030bc },
396 { .start = 0x00a030c0, .end = 0x00a0312c },
397 { .start = 0x00a03c00, .end = 0x00a03c5c },
398 { .start = 0x00a04400, .end = 0x00a04454 },
399 { .start = 0x00a04460, .end = 0x00a04474 },
400 { .start = 0x00a044c0, .end = 0x00a044ec },
401 { .start = 0x00a04500, .end = 0x00a04504 },
402 { .start = 0x00a04510, .end = 0x00a04538 },
403 { .start = 0x00a04540, .end = 0x00a04548 },
404 { .start = 0x00a04560, .end = 0x00a0457c },
405 { .start = 0x00a04590, .end = 0x00a04598 },
406 { .start = 0x00a045c0, .end = 0x00a045f4 },
410 { .start = 0x00a05c00, .end = 0x00a05c18 },
411 { .start = 0x00a05400, .end = 0x00a056e8 },
412 { .start = 0x00a08000, .end = 0x00a098bc },
413 { .start = 0x00a02400, .end = 0x00a02758 },
414 { .start = 0x00a04764, .end = 0x00a0476c },
415 { .start = 0x00a04770, .end = 0x00a04774 },
416 { .start = 0x00a04620, .end = 0x00a04624 },
420 { .start = 0x00a00000, .end = 0x00a00000 },
421 { .start = 0x00a0000c, .end = 0x00a00024 },
422 { .start = 0x00a0002c, .end = 0x00a00034 },
423 { .start = 0x00a0003c, .end = 0x00a0003c },
424 { .start = 0x00a00410, .end = 0x00a00418 },
425 { .start = 0x00a00420, .end = 0x00a00420 },
426 { .start = 0x00a00428, .end = 0x00a00428 },
427 { .start = 0x00a00430, .end = 0x00a0043c },
428 { .start = 0x00a00444, .end = 0x00a00444 },
429 { .start = 0x00a00840, .end = 0x00a00840 },
430 { .start = 0x00a00850, .end = 0x00a00858 },
431 { .start = 0x00a01004, .end = 0x00a01008 },
432 { .start = 0x00a01010, .end = 0x00a01010 },
433 { .start = 0x00a01018, .end = 0x00a01018 },
434 { .start = 0x00a01024, .end = 0x00a01024 },
435 { .start = 0x00a0102c, .end = 0x00a01034 },
436 { .start = 0x00a0103c, .end = 0x00a01040 },
437 { .start = 0x00a01048, .end = 0x00a01050 },
438 { .start = 0x00a01058, .end = 0x00a01058 },
439 { .start = 0x00a01060, .end = 0x00a01070 },
440 { .start = 0x00a0108c, .end = 0x00a0108c },
441 { .start = 0x00a01c20, .end = 0x00a01c28 },
442 { .start = 0x00a01d10, .end = 0x00a01d10 },
443 { .start = 0x00a01e28, .end = 0x00a01e2c },
444 { .start = 0x00a01e60, .end = 0x00a01e60 },
445 { .start = 0x00a01e80, .end = 0x00a01e80 },
446 { .start = 0x00a01ea0, .end = 0x00a01ea0 },
447 { .start = 0x00a02000, .end = 0x00a0201c },
448 { .start = 0x00a02024, .end = 0x00a02024 },
449 { .start = 0x00a02040, .end = 0x00a02048 },
450 { .start = 0x00a020c0, .end = 0x00a020e0 },
451 { .start = 0x00a02400, .end = 0x00a02404 },
452 { .start = 0x00a0240c, .end = 0x00a02414 },
453 { .start = 0x00a0241c, .end = 0x00a0243c },
454 { .start = 0x00a02448, .end = 0x00a024bc },
455 { .start = 0x00a024c4, .end = 0x00a024cc },
456 { .start = 0x00a02508, .end = 0x00a02508 },
457 { .start = 0x00a02510, .end = 0x00a02514 },
458 { .start = 0x00a0251c, .end = 0x00a0251c },
459 { .start = 0x00a0252c, .end = 0x00a0255c },
460 { .start = 0x00a02564, .end = 0x00a025a0 },
461 { .start = 0x00a025a8, .end = 0x00a025b4 },
462 { .start = 0x00a025c0, .end = 0x00a025c0 },
463 { .start = 0x00a025e8, .end = 0x00a025f4 },
464 { .start = 0x00a02c08, .end = 0x00a02c18 },
465 { .start = 0x00a02c2c, .end = 0x00a02c38 },
466 { .start = 0x00a02c68, .end = 0x00a02c78 },
467 { .start = 0x00a03000, .end = 0x00a03000 },
468 { .start = 0x00a03010, .end = 0x00a03014 },
469 { .start = 0x00a0301c, .end = 0x00a0302c },
470 { .start = 0x00a03034, .end = 0x00a03038 },
471 { .start = 0x00a03040, .end = 0x00a03044 },
472 { .start = 0x00a03060, .end = 0x00a03068 },
473 { .start = 0x00a03070, .end = 0x00a03070 },
474 { .start = 0x00a0307c, .end = 0x00a03084 },
475 { .start = 0x00a0308c, .end = 0x00a03090 },
476 { .start = 0x00a03098, .end = 0x00a03098 },
477 { .start = 0x00a030a0, .end = 0x00a030a0 },
478 { .start = 0x00a030a8, .end = 0x00a030b4 },
479 { .start = 0x00a030bc, .end = 0x00a030c0 },
480 { .start = 0x00a030c8, .end = 0x00a030f4 },
481 { .start = 0x00a03100, .end = 0x00a0312c },
482 { .start = 0x00a03c00, .end = 0x00a03c5c },
483 { .start = 0x00a04400, .end = 0x00a04454 },
484 { .start = 0x00a04460, .end = 0x00a04474 },
485 { .start = 0x00a044c0, .end = 0x00a044ec },
486 { .start = 0x00a04500, .end = 0x00a04504 },
487 { .start = 0x00a04510, .end = 0x00a04538 },
488 { .start = 0x00a04540, .end = 0x00a04548 },
489 { .start = 0x00a04560, .end = 0x00a04560 },
490 { .start = 0x00a04570, .end = 0x00a0457c },
491 { .start = 0x00a04590, .end = 0x00a04590 },
492 { .start = 0x00a04598, .end = 0x00a04598 },
493 { .start = 0x00a045c0, .end = 0x00a045f4 },
494 { .start = 0x00a05c18, .end = 0x00a05c1c },
495 { .start = 0x00a0c000, .end = 0x00a0c018 },
496 { .start = 0x00a0c020, .end = 0x00a0c028 },
497 { .start = 0x00a0c038, .end = 0x00a0c094 },
498 { .start = 0x00a0c0c0, .end = 0x00a0c104 },
499 { .start = 0x00a0c10c, .end = 0x00a0c118 },
500 { .start = 0x00a0c150, .end = 0x00a0c174 },
501 { .start = 0x00a0c17c, .end = 0x00a0c188 },
502 { .start = 0x00a0c190, .end = 0x00a0c198 },
503 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 },
504 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 },
508 { .start = 0x00d03c00, .end = 0x00d03c64 },
509 { .start = 0x00d05c18, .end = 0x00d05c1c },
510 { .start = 0x00d0c000, .end = 0x00d0c174 },
518 for (i = 0; i < len_bytes; i += 4)
540 for (i = 0; i < range_len; i++) {
596 sg_set_page(iter, new_page, alloc_size, 0);
611 for (i = 0; i < range_len; i++) {
674 while (0)
681 u32 fifo_len = 0;
685 return 0;
694 for (i = 0; i < mem_cfg->num_lmacs; i++)
705 u32 fifo_len = 0;
715 for (i = 0; i < mem_cfg->num_lmacs; i++) {
718 for (j = 0; j < mem_cfg->num_txfifo_entries; j++)
729 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++)
784 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0;
785 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;
787 0 : fwrt->trans->cfg->dccm2_len;
839 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++)
895 dump_info->lmac_err_id[0] =
896 cpu_to_le32(fwrt->dump.lmac_err_id[0]);
913 for (i = 0; i < MAX_NUM_LMAC; i++) {
917 for (j = 0; j < TX_FIFO_MAX_NUM; j++)
927 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) {
968 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
1041 for (i = 0; i < le32_to_cpu(size); i += 4)
1102 for (i = 0; i < le32_to_cpu(size); i += 4) {
1161 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4)
1181 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1186 if (ret < 0)
1305 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]);
1309 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n",
1314 iter->internal_txf = 0;
1315 iter->fifo_size = 0;
1320 iter->lmac = 0;
1379 for (i = 0; i < registers_num; i++) {
1404 for (i = 0; i < iter->fifo_size; i += sizeof(*data))
1442 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) {
1475 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]);
1482 memset(data, 0, sizeof(*data));
1502 SHARED_MEM_CFG_CMD, 0) <= 3)
1503 max_idx = 0;
1517 case 0:
1546 rxf_data.size = 0;
1563 for (i = 0; i < registers_num; i++) {
1581 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1);
1583 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1);
1586 0x0);
1591 for (i = 0; i < rxf_data.size; i += sizeof(*data))
1655 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) {
1750 * DBGC1 address + (0x100 * i)
1752 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100;
1755 return 0;
1897 return 0;
1909 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
1914 for (i = 0; i < fw_mon->num_frags; i++) {
1927 u32 num_of_fifos = 0;
1951 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) {
1955 return 0;
1969 return 0;
1986 return 0;
1988 for (range = 0; range < ranges; range++)
2020 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id);
2025 for (i = 0; i < fw_mon->num_frags; i++) {
2049 return 0;
2065 return 0;
2077 u32 size = 0;
2089 return 0;
2108 rx_data.size = 0;
2148 u32 size = 0;
2151 return 0;
2165 u32 ranges = 0;
2170 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) {
2174 return 0;
2179 return 0;
2218 * Returns: the size of the current dump tlv or 0 if failed
2248 return 0;
2254 return 0;
2260 return 0;
2267 return 0;
2274 return 0;
2279 return 0;
2324 for (i = 0; i < num_of_ranges; i++) {
2328 if (range_size < 0) {
2353 return 0;
2366 u32 num_of_cfg_names = 0;
2376 return 0;
2398 * Several HWs all have type == 0x42, so we'll override this value
2470 return 0;
2474 return 0;
2623 u32 size = 0;
2631 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) {
2720 return 0;
2724 return 0;
2731 return 0;
2749 fwrt->dump.lmac_err_id[0] = 0;
2751 fwrt->dump.lmac_err_id[1] = 0;
2752 fwrt->dump.umac_err_id = 0;
2787 fw_error_dump.fwrt_len, 0);
2837 u32 offs = 0;
2867 return 0;
2873 * so check against ~0UL first.
2875 if (fwrt->dump.active_wks == ~0UL)
2898 return 0;
2927 iwl_dump_error_desc->len = 0;
2930 false, 0);
2939 return 0;
2949 unsigned int delay = 0;
2956 return 0;
2962 return 0;
2989 int ret, len = 0;
2993 return 0;
2998 buf[sizeof(buf) - 1] = '\0';
3006 buf[sizeof(buf) - 1] = '\0';
3017 return 0;
3035 return 0;
3046 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {
3064 return 0;
3075 .data[0] = &hcmd_data,
3076 .len[0] = sizeof(hcmd_data),
3095 struct iwl_fw_dbg_params params = {0};
3135 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0);
3171 return 0;
3177 * so check against ~0UL first.
3179 if (fwrt->dump.active_wks == ~0UL)
3191 delay = 0;
3204 return 0;
3261 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++)
3277 .data[0] = &cmd,
3278 .len[0] = sizeof(cmd),
3288 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
3297 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0);
3302 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0);
3312 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
3313 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
3314 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1);
3320 return 0;
3354 hcmd.data[0] = ▮
3355 hcmd.len[0] = sizeof(marker);
3372 int ret __maybe_unused = 0;
3406 .data[0] = &cmd,
3407 .len[0] = sizeof(cmd),
3425 struct iwl_fw_dbg_params params = {0};