Lines Matching +full:host2wbm +full:- +full:desc +full:- +full:feed
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
38 * 4K - 32 = 0xFE0
68 "mhi-er0",
69 "mhi-er1",
86 "host2wbm-desc-feed",
87 "host2reo-re-injection",
88 "host2reo-command",
89 "host2rxdma-monitor-ring3",
90 "host2rxdma-monitor-ring2",
91 "host2rxdma-monitor-ring1",
92 "reo2ost-exception",
93 "wbm2host-rx-release",
94 "reo2host-status",
95 "reo2host-destination-ring4",
96 "reo2host-destination-ring3",
97 "reo2host-destination-ring2",
98 "reo2host-destination-ring1",
99 "rxdma2host-monitor-destination-mac3",
100 "rxdma2host-monitor-destination-mac2",
101 "rxdma2host-monitor-destination-mac1",
102 "ppdu-end-interrupts-mac3",
103 "ppdu-end-interrupts-mac2",
104 "ppdu-end-interrupts-mac1",
105 "rxdma2host-monitor-status-ring-mac3",
106 "rxdma2host-monitor-status-ring-mac2",
107 "rxdma2host-monitor-status-ring-mac1",
108 "host2rxdma-host-buf-ring-mac3",
109 "host2rxdma-host-buf-ring-mac2",
110 "host2rxdma-host-buf-ring-mac1",
111 "rxdma2host-destination-ring-mac3",
112 "rxdma2host-destination-ring-mac2",
113 "rxdma2host-destination-ring-mac1",
114 "host2tcl-input-ring4",
115 "host2tcl-input-ring3",
116 "host2tcl-input-ring2",
117 "host2tcl-input-ring1",
118 "wbm2host-tx-completions-ring4",
119 "wbm2host-tx-completions-ring3",
120 "wbm2host-tx-completions-ring2",
121 "wbm2host-tx-completions-ring1",
122 "tcl2host-status-ring",
129 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); in ath12k_pci_bus_wake_up()
136 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); in ath12k_pci_bus_release()
151 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_select_window()
156 lockdep_assert_held(&ab_pci->window_lock); in ath12k_pci_select_window()
159 static_window = ab_pci->register_window & WINDOW_STATIC_MASK; in ath12k_pci_select_window()
162 if (window != ab_pci->register_window) { in ath12k_pci_select_window()
165 ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_window()
166 ioread32(ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_window()
168 (char *)ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_window()
169 ioread32((char *)ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_window()
171 ab_pci->register_window = window; in ath12k_pci_select_window()
183 spin_lock_bh(&ab_pci->window_lock); in ath12k_pci_select_static_window()
184 ab_pci->register_window = window; in ath12k_pci_select_static_window()
185 spin_unlock_bh(&ab_pci->window_lock); in ath12k_pci_select_static_window()
188 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_static_window()
190 iowrite32(WINDOW_ENABLE_BIT | window, (char *)ab_pci->ab->mem + WINDOW_REG_ADDRESS); in ath12k_pci_select_static_window()
345 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_free_ext_irq()
347 for (j = 0; j < irq_grp->num_irq; j++) in ath12k_pci_free_ext_irq()
348 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); in ath12k_pci_free_ext_irq()
350 netif_napi_del(&irq_grp->napi); in ath12k_pci_free_ext_irq()
358 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_free_irq()
362 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); in ath12k_pci_free_irq()
373 enable_irq(ab->irq_num[irq_idx]); in ath12k_pci_ce_irq_enable()
381 disable_irq_nosync(ab->irq_num[irq_idx]); in ath12k_pci_ce_irq_disable()
388 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_ce_irqs_disable()
400 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_sync_ce_irqs()
405 synchronize_irq(ab->irq_num[irq_idx]); in ath12k_pci_sync_ce_irqs()
413 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); in ath12k_pci_ce_tasklet()
415 ath12k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); in ath12k_pci_ce_tasklet()
423 ce_pipe->timestamp = jiffies; in ath12k_pci_ce_interrupt_handler()
425 ath12k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); in ath12k_pci_ce_interrupt_handler()
426 tasklet_schedule(&ce_pipe->intr_tq); in ath12k_pci_ce_interrupt_handler()
435 for (i = 0; i < irq_grp->num_irq; i++) in ath12k_pci_ext_grp_disable()
436 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath12k_pci_ext_grp_disable()
444 struct ath12k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i]; in __ath12k_pci_ext_irq_disable()
448 napi_synchronize(&irq_grp->napi); in __ath12k_pci_ext_irq_disable()
449 napi_disable(&irq_grp->napi); in __ath12k_pci_ext_irq_disable()
457 for (i = 0; i < irq_grp->num_irq; i++) in ath12k_pci_ext_grp_enable()
458 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath12k_pci_ext_grp_enable()
466 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_sync_ext_irqs()
468 for (j = 0; j < irq_grp->num_irq; j++) { in ath12k_pci_sync_ext_irqs()
469 irq_idx = irq_grp->irqs[j]; in ath12k_pci_sync_ext_irqs()
470 synchronize_irq(ab->irq_num[irq_idx]); in ath12k_pci_sync_ext_irqs()
480 struct ath12k_base *ab = irq_grp->ab; in ath12k_pci_ext_grp_napi_poll()
499 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq); in ath12k_pci_ext_interrupt_handler()
502 irq_grp->timestamp = jiffies; in ath12k_pci_ext_interrupt_handler()
506 napi_schedule(&irq_grp->napi); in ath12k_pci_ext_interrupt_handler()
525 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_ext_irq_config()
528 irq_grp->ab = ab; in ath12k_pci_ext_irq_config()
529 irq_grp->grp_id = i; in ath12k_pci_ext_irq_config()
530 init_dummy_netdev(&irq_grp->napi_ndev); in ath12k_pci_ext_irq_config()
531 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, in ath12k_pci_ext_irq_config()
534 if (ab->hw_params->ring_mask->tx[i] || in ath12k_pci_ext_irq_config()
535 ab->hw_params->ring_mask->rx[i] || in ath12k_pci_ext_irq_config()
536 ab->hw_params->ring_mask->rx_err[i] || in ath12k_pci_ext_irq_config()
537 ab->hw_params->ring_mask->rx_wbm_rel[i] || in ath12k_pci_ext_irq_config()
538 ab->hw_params->ring_mask->reo_status[i] || in ath12k_pci_ext_irq_config()
539 ab->hw_params->ring_mask->host2rxdma[i] || in ath12k_pci_ext_irq_config()
540 ab->hw_params->ring_mask->rx_mon_dest[i]) { in ath12k_pci_ext_irq_config()
544 irq_grp->num_irq = num_irq; in ath12k_pci_ext_irq_config()
545 irq_grp->irqs[0] = base_idx + i; in ath12k_pci_ext_irq_config()
547 for (j = 0; j < irq_grp->num_irq; j++) { in ath12k_pci_ext_irq_config()
548 int irq_idx = irq_grp->irqs[j]; in ath12k_pci_ext_irq_config()
550 int irq = ath12k_pci_get_msi_irq(ab->dev, vector); in ath12k_pci_ext_irq_config()
552 ab->irq_num[irq_idx] = irq; in ath12k_pci_ext_irq_config()
567 disable_irq_nosync(ab->irq_num[irq_idx]); in ath12k_pci_ext_irq_config()
591 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_config_irq()
596 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data); in ath12k_pci_config_irq()
597 ce_pipe = &ab->ce.ce_pipe[i]; in ath12k_pci_config_irq()
601 tasklet_setup(&ce_pipe->intr_tq, ath12k_pci_ce_tasklet); in ath12k_pci_config_irq()
612 ab->irq_num[irq_idx] = irq; in ath12k_pci_config_irq()
627 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; in ath12k_pci_init_qmi_ce_config()
629 cfg->tgt_ce = ab->hw_params->target_ce_config; in ath12k_pci_init_qmi_ce_config()
630 cfg->tgt_ce_len = ab->hw_params->target_ce_count; in ath12k_pci_init_qmi_ce_config()
632 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map; in ath12k_pci_init_qmi_ce_config()
633 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len; in ath12k_pci_init_qmi_ce_config()
634 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id; in ath12k_pci_init_qmi_ce_config()
641 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_ce_irqs_enable()
650 struct pci_dev *dev = ab_pci->pdev; in ath12k_pci_msi_config()
653 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); in ath12k_pci_msi_config()
660 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); in ath12k_pci_msi_config()
675 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_msi_alloc()
676 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; in ath12k_pci_msi_alloc()
681 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, in ath12k_pci_msi_alloc()
682 msi_config->total_vectors, in ath12k_pci_msi_alloc()
683 msi_config->total_vectors, in ath12k_pci_msi_alloc()
685 if (num_vectors != msi_config->total_vectors) { in ath12k_pci_msi_alloc()
687 msi_config->total_vectors, num_vectors); in ath12k_pci_msi_alloc()
690 return -EINVAL; in ath12k_pci_msi_alloc()
697 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); in ath12k_pci_msi_alloc()
700 ret = -EINVAL; in ath12k_pci_msi_alloc()
704 ab_pci->msi_ep_base_data = msi_desc->msg.data; in ath12k_pci_msi_alloc()
705 if (msi_desc->pci.msi_attrib.is_64) in ath12k_pci_msi_alloc()
706 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); in ath12k_pci_msi_alloc()
708 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); in ath12k_pci_msi_alloc()
713 pci_free_irq_vectors(ab_pci->pdev); in ath12k_pci_msi_alloc()
720 pci_free_irq_vectors(ab_pci->pdev); in ath12k_pci_msi_free()
725 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_claim()
730 if (device_id != ab_pci->dev_id) { in ath12k_pci_claim()
732 device_id, ab_pci->dev_id); in ath12k_pci_claim()
733 ret = -EIO; in ath12k_pci_claim()
755 ret = dma_set_mask_and_coherent(&pdev->dev, in ath12k_pci_claim()
765 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM); in ath12k_pci_claim()
766 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0); in ath12k_pci_claim()
767 if (!ab->mem) { in ath12k_pci_claim()
769 ret = -EIO; in ath12k_pci_claim()
773 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); in ath12k_pci_claim()
786 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_free_region()
787 struct pci_dev *pci_dev = ab_pci->pdev; in ath12k_pci_free_region()
789 pci_iounmap(pci_dev, ab->mem); in ath12k_pci_free_region()
790 ab->mem = NULL; in ath12k_pci_free_region()
798 struct ath12k_base *ab = ab_pci->ab; in ath12k_pci_aspm_disable()
800 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, in ath12k_pci_aspm_disable()
801 &ab_pci->link_ctl); in ath12k_pci_aspm_disable()
804 ab_pci->link_ctl, in ath12k_pci_aspm_disable()
805 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), in ath12k_pci_aspm_disable()
806 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); in ath12k_pci_aspm_disable()
809 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, in ath12k_pci_aspm_disable()
810 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); in ath12k_pci_aspm_disable()
812 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags); in ath12k_pci_aspm_disable()
817 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) in ath12k_pci_aspm_restore()
818 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, in ath12k_pci_aspm_restore()
819 ab_pci->link_ctl); in ath12k_pci_aspm_restore()
826 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_kill_tasklets()
827 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; in ath12k_pci_kill_tasklets()
832 tasklet_kill(&ce_pipe->intr_tq); in ath12k_pci_kill_tasklets()
850 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) { in ath12k_pci_map_service_to_pipe()
851 entry = &ab->hw_params->svc_to_ce_map[i]; in ath12k_pci_map_service_to_pipe()
853 if (__le32_to_cpu(entry->service_id) != service_id) in ath12k_pci_map_service_to_pipe()
856 switch (__le32_to_cpu(entry->pipedir)) { in ath12k_pci_map_service_to_pipe()
861 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
866 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
872 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
873 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath12k_pci_map_service_to_pipe()
881 return -ENOENT; in ath12k_pci_map_service_to_pipe()
898 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; in ath12k_pci_get_user_msi_assignment()
901 for (idx = 0; idx < msi_config->total_users; idx++) { in ath12k_pci_get_user_msi_assignment()
902 if (strcmp(user_name, msi_config->users[idx].name) == 0) { in ath12k_pci_get_user_msi_assignment()
903 *num_vectors = msi_config->users[idx].num_vectors; in ath12k_pci_get_user_msi_assignment()
904 *user_base_data = msi_config->users[idx].base_vector in ath12k_pci_get_user_msi_assignment()
905 + ab_pci->msi_ep_base_data; in ath12k_pci_get_user_msi_assignment()
906 *base_vector = msi_config->users[idx].base_vector; in ath12k_pci_get_user_msi_assignment()
918 return -EINVAL; in ath12k_pci_get_user_msi_assignment()
925 struct pci_dev *pci_dev = to_pci_dev(ab->dev); in ath12k_pci_get_msi_address()
927 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, in ath12k_pci_get_msi_address()
930 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { in ath12k_pci_get_msi_address()
931 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, in ath12k_pci_get_msi_address()
943 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { in ath12k_pci_get_ce_msi_idx()
970 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath12k_pci_ext_irq_enable()
972 napi_enable(&irq_grp->napi); in ath12k_pci_ext_irq_enable()
1011 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); in ath12k_pci_start()
1027 /* for offset beyond BAR + 4K - 32, may in ath12k_pci_read32()
1030 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_read32()
1031 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) in ath12k_pci_read32()
1032 ret = ab_pci->pci_ops->wakeup(ab); in ath12k_pci_read32()
1036 val = ioread32(ab->mem + offset); in ath12k_pci_read32()
1038 val = ioread32((char *)ab->mem + offset); in ath12k_pci_read32()
1041 if (ab->static_window_map) in ath12k_pci_read32()
1047 spin_lock_bh(&ab_pci->window_lock); in ath12k_pci_read32()
1050 val = ioread32(ab->mem + window_start + in ath12k_pci_read32()
1052 val = ioread32((char *)ab->mem + window_start + in ath12k_pci_read32()
1055 spin_unlock_bh(&ab_pci->window_lock); in ath12k_pci_read32()
1060 offset = offset - PCI_MHIREGLEN_REG; in ath12k_pci_read32()
1063 val = ioread32(ab->mem + window_start + in ath12k_pci_read32()
1065 val = ioread32((char *)ab->mem + window_start + in ath12k_pci_read32()
1071 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_read32()
1072 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && in ath12k_pci_read32()
1074 ab_pci->pci_ops->release(ab); in ath12k_pci_read32()
1084 /* for offset beyond BAR + 4K - 32, may in ath12k_pci_write32()
1087 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_write32()
1088 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) in ath12k_pci_write32()
1089 ret = ab_pci->pci_ops->wakeup(ab); in ath12k_pci_write32()
1093 iowrite32(value, ab->mem + offset); in ath12k_pci_write32()
1095 iowrite32(value, (char *)ab->mem + offset); in ath12k_pci_write32()
1098 if (ab->static_window_map) in ath12k_pci_write32()
1104 spin_lock_bh(&ab_pci->window_lock); in ath12k_pci_write32()
1107 iowrite32(value, ab->mem + window_start + in ath12k_pci_write32()
1109 iowrite32(value, (char *)ab->mem + window_start + in ath12k_pci_write32()
1112 spin_unlock_bh(&ab_pci->window_lock); in ath12k_pci_write32()
1117 offset = offset - PCI_MHIREGLEN_REG; in ath12k_pci_write32()
1120 iowrite32(value, ab->mem + window_start + in ath12k_pci_write32()
1122 iowrite32(value, (char *)ab->mem + window_start + in ath12k_pci_write32()
1128 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && in ath12k_pci_write32()
1129 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && in ath12k_pci_write32()
1131 ab_pci->pci_ops->release(ab); in ath12k_pci_write32()
1139 ab_pci->register_window = 0; in ath12k_pci_power_up()
1140 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); in ath12k_pci_power_up()
1141 ath12k_pci_sw_reset(ab_pci->ab, true); in ath12k_pci_power_up()
1156 if (ab->static_window_map) in ath12k_pci_power_up()
1169 ath12k_pci_force_wake(ab_pci->ab); in ath12k_pci_power_down()
1172 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); in ath12k_pci_power_down()
1173 ath12k_pci_sw_reset(ab_pci->ab, false); in ath12k_pci_power_down()
1219 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI); in ath12k_pci_probe()
1221 dev_err(&pdev->dev, "failed to allocate ath12k base\n"); in ath12k_pci_probe()
1222 return -ENOMEM; in ath12k_pci_probe()
1225 ab->dev = &pdev->dev; in ath12k_pci_probe()
1228 ab_pci->dev_id = pci_dev->device; in ath12k_pci_probe()
1229 ab_pci->ab = ab; in ath12k_pci_probe()
1230 ab_pci->pdev = pdev; in ath12k_pci_probe()
1231 ab->hif.ops = &ath12k_pci_hif_ops; in ath12k_pci_probe()
1233 spin_lock_init(&ab_pci->window_lock); in ath12k_pci_probe()
1241 switch (pci_dev->device) { in ath12k_pci_probe()
1243 ab_pci->msi_config = &ath12k_msi_config[0]; in ath12k_pci_probe()
1244 ab->static_window_map = true; in ath12k_pci_probe()
1245 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274; in ath12k_pci_probe()
1250 ab->hw_rev = ATH12K_HW_QCN9274_HW20; in ath12k_pci_probe()
1253 ab->hw_rev = ATH12K_HW_QCN9274_HW10; in ath12k_pci_probe()
1256 dev_err(&pdev->dev, in ath12k_pci_probe()
1259 ret = -EOPNOTSUPP; in ath12k_pci_probe()
1264 ab_pci->msi_config = &ath12k_msi_config[0]; in ath12k_pci_probe()
1265 ab->static_window_map = false; in ath12k_pci_probe()
1266 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850; in ath12k_pci_probe()
1271 ab->hw_rev = ATH12K_HW_WCN7850_HW20; in ath12k_pci_probe()
1274 dev_err(&pdev->dev, in ath12k_pci_probe()
1277 ret = -EOPNOTSUPP; in ath12k_pci_probe()
1283 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", in ath12k_pci_probe()
1284 pci_dev->device); in ath12k_pci_probe()
1285 ret = -EOPNOTSUPP; in ath12k_pci_probe()
1359 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) { in ath12k_pci_remove()
1365 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags); in ath12k_pci_remove()
1367 cancel_work_sync(&ab->reset_work); in ath12k_pci_remove()