Lines Matching +full:3 +full:- +full:ring
1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
21 #define HAL_MAX_AVAIL_BLK_RES 3
28 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \
57 /* SW2TCL(x) R0 ring configuration address */
62 #define HAL_TCL1_RING_ID(ab) ((ab)->hw_params->regs->hal_tcl1_ring_id)
64 ((ab)->hw_params->regs->hal_tcl1_ring_misc)
66 ((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_lsb)
68 ((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_msb)
70 ((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix0)
72 ((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix1)
74 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_lsb)
76 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_msb)
78 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_data)
81 ((ab)->hw_params->regs->hal_tcl_ring_base_lsb)
84 (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB)
86 (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB)
88 (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB)
90 (HAL_TCL1_RING_BASE_MSB - HAL_TCL1_RING_BASE_LSB)
92 (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB)
94 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB)
96 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB)
98 (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB)
100 (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB)
102 (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB)
104 /* SW2TCL(x) R2 ring pointers (head/tail) address */
111 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP)
113 /* TCL STATUS ring address */
115 ((ab)->hw_params->regs->hal_tcl_status_ring_base_lsb)
118 /* PPE2TCL1 Ring address */
122 /* WBM PPE Release Ring address */
124 ((ab)->hw_params->regs->hal_ppe_rel_ring_base)
127 /* REO2SW(x) R0 ring configuration address */
130 ((ab)->hw_params->regs->hal_reo1_misc_ctrl_addr)
135 #define HAL_REO1_SW_COOKIE_CFG0(ab) ((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg0)
136 #define HAL_REO1_SW_COOKIE_CFG1(ab) ((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg1)
137 #define HAL_REO1_QDESC_LUT_BASE0(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_lut_base0)
138 #define HAL_REO1_QDESC_LUT_BASE1(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_lut_base1)
139 #define HAL_REO1_RING_BASE_LSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_base_lsb)
140 #define HAL_REO1_RING_BASE_MSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_base_msb)
141 #define HAL_REO1_RING_ID(ab) ((ab)->hw_params->regs->hal_reo1_ring_id)
142 #define HAL_REO1_RING_MISC(ab) ((ab)->hw_params->regs->hal_reo1_ring_misc)
143 #define HAL_REO1_RING_HP_ADDR_LSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_hp_addr_lsb)
144 #define HAL_REO1_RING_HP_ADDR_MSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_hp_addr_msb)
146 ((ab)->hw_params->regs->hal_reo1_ring_producer_int_setup)
148 ((ab)->hw_params->regs->hal_reo1_ring_msi1_base_lsb)
150 ((ab)->hw_params->regs->hal_reo1_ring_msi1_base_msb)
151 #define HAL_REO1_RING_MSI1_DATA(ab) ((ab)->hw_params->regs->hal_reo1_ring_msi1_data)
152 #define HAL_REO2_RING_BASE_LSB(ab) ((ab)->hw_params->regs->hal_reo2_ring_base)
153 #define HAL_REO1_AGING_THRESH_IX_0(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix0)
154 #define HAL_REO1_AGING_THRESH_IX_1(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix1)
155 #define HAL_REO1_AGING_THRESH_IX_2(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix2)
156 #define HAL_REO1_AGING_THRESH_IX_3(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix3)
158 /* REO2SW(x) R2 ring pointers (head/tail) address */
163 #define HAL_REO1_RING_TP_OFFSET (HAL_REO1_RING_TP - HAL_REO1_RING_HP)
165 /* REO2SW0 ring configuration address */
167 ((ab)->hw_params->regs->hal_reo2_sw0_ring_base)
169 /* REO2SW0 R2 ring pointer (head/tail) address */
174 ((ab)->hw_params->regs->hal_reo_cmd_ring_base)
181 ((ab)->hw_params->regs->hal_sw2reo_ring_base)
183 ((ab)->hw_params->regs->hal_sw2reo1_ring_base)
189 /* CE ring R0 address */
195 /* CE ring R2 address */
201 ((ab)->hw_params->regs->hal_reo_status_ring_base)
206 ((ab)->hw_params->regs->hal_wbm_idle_ring_base_lsb)
208 ((ab)->hw_params->regs->hal_wbm_idle_ring_misc_addr)
210 ((ab)->hw_params->regs->hal_wbm_r0_idle_list_cntl_addr)
212 ((ab)->hw_params->regs->hal_wbm_r0_idle_list_size_addr)
214 ((ab)->hw_params->regs->hal_wbm_scattered_ring_base_lsb)
216 ((ab)->hw_params->regs->hal_wbm_scattered_ring_base_msb)
218 ((ab)->hw_params->regs->hal_wbm_scattered_desc_head_info_ix0)
220 ((ab)->hw_params->regs->hal_wbm_scattered_desc_head_info_ix1)
222 ((ab)->hw_params->regs->hal_wbm_scattered_desc_tail_info_ix0)
224 ((ab)->hw_params->regs->hal_wbm_scattered_desc_tail_info_ix1)
226 ((ab)->hw_params->regs->hal_wbm_scattered_desc_ptr_hp_addr)
233 ((ab)->hw_params->regs->hal_wbm_sw_release_ring_base_lsb)
235 ((ab)->hw_params->regs->hal_wbm_sw1_release_ring_base_lsb)
243 ((ab)->hw_params->regs->hal_wbm0_release_ring_base_lsb)
246 ((ab)->hw_params->regs->hal_wbm1_release_ring_base_lsb)
264 #define HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN BIT(3)
268 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN BIT(3)
273 /* TCL ring field mask and offset */
279 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3)
291 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3)
299 /* REO ring field mask and offset */
304 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3)
315 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3)
323 /* CE ring bit field mask and shift */
330 /* WBM ring bit field mask and shift */
363 #define HAL_WBM2SW_REL_ERR_RING_NUM 3
460 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, /* RX ERROR RING */
500 #define HAL_SRNG_NUM_PMACS 3
501 #define HAL_SRNG_NUM_DMAC_RINGS (HAL_SRNG_RING_ID_DMAC_CMN_ID_END - \
503 #define HAL_SRNG_RINGS_PER_PMAC (HAL_SRNG_RING_ID_PMAC1_ID_END - \
557 HAL_REO_CMD_UNBLOCK_CACHE = 3,
576 HAL_REO_CMD_RESOURCE_BLOCKED = 3,
620 /* Common SRNG ring structure for source and destination rings */
622 /* Unique SRNG ring ID */
625 /* Ring initialization done */
628 /* Interrupt/MSI value assigned to this ring */
631 /* Physical base address of the ring */
634 /* Virtual base address of the ring */
637 /* Number of entries in ring */
640 /* Ring size */
643 /* Ring size mask */
646 /* Size of ring entry */
649 /* Interrupt timer threshold - in micro seconds */
652 /* Interrupt batch counter threshold - in number of ring entries */
670 /* Lock for serializing ring index updates */
675 /* Start offset of SRNG register groups for this ring
676 * TBD: See if this is required - register address can be derived
677 * from ring ID
683 /* Source or Destination ring */
697 /* Tail pointer location to be updated by SW - This
726 /* Head pointer location to be updated by SW - This
732 /* Low threshold - in number of ring entries */
741 /* Interrupt mitigation - Batch threshold in terms of number of frames */
746 /* Interrupt mitigation - timer threshold in us */
774 * descriptor list, where the chip 0 WBM is chosen in case of a multi-chip config
776 * descriptor list, where the chip 1 WBM is chosen in case of a multi-chip config
778 * descriptor list, where the chip 2 WBM is chosen in case of a multi-chip config
780 * @HAL_RX_BUF_RBM_SW0_BM: For ring 0 -- returned to host
781 * @HAL_RX_BUF_RBM_SW1_BM: For ring 1 -- returned to host
782 * @HAL_RX_BUF_RBM_SW2_BM: For ring 2 -- returned to host
783 * @HAL_RX_BUF_RBM_SW3_BM: For ring 3 -- returned to host
784 * @HAL_RX_BUF_RBM_SW4_BM: For ring 4 -- returned to host
785 * @HAL_RX_BUF_RBM_SW5_BM: For ring 5 -- returned to host
786 * @HAL_RX_BUF_RBM_SW6_BM: For ring 6 -- returned to host
809 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3)
896 #define HAL_HASH_ROUTING_RING_SW3 3
914 u32 rx_bitmap[8]; /* Bitmap from 0-255 */
1012 /* Shared memory for ring pointer updates from host to FW */
1028 /* Maps WBM ring number and Return Buffer Manager Id per TCL ring */