1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
61 /* PHY config registers  - write */
67 /* PHY config registers  - read */
76 	{"rockchip,rk3399-pcie-phy",	1},
89 #define	PHY_LOCK(_sc)		mtx_lock(&(_sc)->mtx)
90 #define	PHY_UNLOCK(_sc)		mtx_unlock(&(_sc)->mtx)
91 #define	PHY_LOCK_INIT(_sc)	mtx_init(&(_sc)->mtx, 			\
92 	    device_get_nameunit(_sc->dev), "rk_pcie_phyc", MTX_DEF)
93 #define	PHY_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->mtx);
94 #define	PHY_ASSERT_LOCKED(_sc)	mtx_assert(&(_sc)->mtx, MA_OWNED);
95 #define	PHY_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
97 #define	RD4(sc, reg)		SYSCON_READ_4((sc)->syscon, (reg))
99     SYSCON_WRITE_4((sc)->syscon, (reg), ((mask) << GRF_HIWORD_SHIFT) | (val))
115 	DELAY(10);  in cfg_write()
118 	DELAY(10);  in cfg_write()
128 	DELAY(10);  in cfg_read()
141 	sc->enable_count++;  in rk_pcie_phy_up()
142 	if (sc->enable_count != 1) {  in rk_pcie_phy_up()
147 	rv = hwreset_deassert(sc->hwreset_phy);  in rk_pcie_phy_up()
149 		device_printf(sc->dev, "Cannot deassert 'phy' reset\n");  in rk_pcie_phy_up()
153 	/* Un-idle all lanes */  in rk_pcie_phy_up()
157 	/* Wait for PLL lock */  in rk_pcie_phy_up()
158 	for (i = 100; i > 0; i--) {  in rk_pcie_phy_up()
162 		DELAY(1000);  in rk_pcie_phy_up()
165 		device_printf(sc->dev, "PLL lock timeouted, 0x%02X\n", val);  in rk_pcie_phy_up()
174 	/* Wait for ungating of ref clock */  in rk_pcie_phy_up()
175 	for (i = 100; i > 0; i--) {  in rk_pcie_phy_up()
179 		DELAY(1000);  in rk_pcie_phy_up()
182 		device_printf(sc->dev, "PLL output enable timeouted\n");  in rk_pcie_phy_up()
187 	/* Wait for PLL relock (to 5GHz) */  in rk_pcie_phy_up()
188 	for (i = 100; i > 0; i--) {  in rk_pcie_phy_up()
192 		DELAY(1000);  in rk_pcie_phy_up()
195 		device_printf(sc->dev, "PLL relock timeouted\n");  in rk_pcie_phy_up()
212 	if (sc->enable_count <= 0)  in rk_pcie_phy_down()
215 	sc->enable_count--;  in rk_pcie_phy_down()
217 	/* Idle given lane */  in rk_pcie_phy_down()
222 	if (sc->enable_count == 0) {  in rk_pcie_phy_down()
223 		rv = hwreset_assert(sc->hwreset_phy);  in rk_pcie_phy_down()
225 			device_printf(sc->dev, "Cannot assert 'phy' reset\n");  in rk_pcie_phy_down()
268 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in rk_pcie_phy_probe()
285 	sc->dev = dev;  in rk_pcie_phy_attach()
289 	if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 ||  in rk_pcie_phy_attach()
290 	    sc->syscon == NULL) {  in rk_pcie_phy_attach()
303 	rv = clk_get_by_ofw_name(sc->dev, 0, "refclk", &sc->clk_ref);  in rk_pcie_phy_attach()
305 		device_printf(sc->dev, "Cannot get 'refclk' clock\n");  in rk_pcie_phy_attach()
309 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "phy", &sc->hwreset_phy);  in rk_pcie_phy_attach()
311 		device_printf(sc->dev, "Cannot get 'phy' reset\n");  in rk_pcie_phy_attach()
316 	rv = hwreset_assert(sc->hwreset_phy);  in rk_pcie_phy_attach()
318 		device_printf(sc->dev, "Cannot assert 'phy' reset\n");  in rk_pcie_phy_attach()
323 	rv = clk_enable(sc->clk_ref);  in rk_pcie_phy_attach()
325 		device_printf(sc->dev, "Cannot enable 'ref' clock\n");  in rk_pcie_phy_attach()