Lines Matching +full:0 +full:x25c

46 #define	PMC_CNTRL			0x000
47 #define PMC_CNTRL_CPUPWRGOOD_SEL_MASK (0x3 << 20)
68 #define PMC_CNTRL_KBC_CLK_DIS (1 << 0)
70 #define PMC_DPD_SAMPLE 0x020
72 #define PMC_CLAMP_STATUS 0x02C
73 #define PMC_CLAMP_STATUS_PARTID(x) (1 << ((x) & 0x1F))
75 #define PMC_PWRGATE_TOGGLE 0x030
77 #define PMC_PWRGATE_TOGGLE_PARTID(x) (((x) & 0x1F) << 0)
79 #define PMC_REMOVE_CLAMPING_CMD 0x034
80 #define PMC_REMOVE_CLAMPING_CMD_PARTID(x) (1 << ((x) & 0x1F))
82 #define PMC_PWRGATE_STATUS 0x038
83 #define PMC_PWRGATE_STATUS_PARTID(x) (1 << ((x) & 0x1F))
85 #define PMC_SCRATCH0 0x050
93 #define PMC_CPUPWRGOOD_TIMER 0x0c8
94 #define PMC_CPUPWROFF_TIMER 0x0cc
96 #define PMC_SCRATCH41 0x140
98 #define PMC_SENSOR_CTRL 0x1b0
101 #define PMC_SENSOR_CTRL_ENABLE_PG (1 << 0)
103 #define PMC_IO_DPD_REQ 0x1b8
104 #define PMC_IO_DPD_REQ_CODE_IDLE (0 << 30)
109 #define PMC_IO_DPD_STATUS 0x1bc
111 #define PMC_IO_DPD2_REQ 0x1c0
112 #define PMC_IO_DPD2_STATUS 0x1c4
114 #define PMC_SEL_DPD_TIM 0x1c8
116 #define PMC_SCRATCH54 0x258
118 #define PMC_SCRATCH54_ADDR_SHIFT 0
120 #define PMC_SCRATCH55 0x25c
124 #define PMC_SCRATCH55_CNTRL_ID_MASK 0x07
126 #define PMC_SCRATCH55_PINMUX_MASK 0x07
128 #define PMC_SCRATCH55_CHECKSUM_MASK 0xFF
130 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
131 #define PMC_SCRATCH55_I2CSLV1_MASK 0x7F
133 #define PMC_GPU_RG_CNTRL 0x2d4
169 {NULL, 0},
192 if (((reg != 0) && ena) || ((reg == 0) && !ena)) { in tegra124_pmc_set_powergate()
194 return (0); in tegra124_pmc_set_powergate()
197 for (i = 100; i > 0; i--) { in tegra124_pmc_set_powergate()
199 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0) in tegra124_pmc_set_powergate()
203 if (i <= 0) in tegra124_pmc_set_powergate()
210 for (i = 100; i > 0; i--) { in tegra124_pmc_set_powergate()
212 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0) in tegra124_pmc_set_powergate()
216 if (i <= 0) in tegra124_pmc_set_powergate()
220 return (0); in tegra124_pmc_set_powergate()
234 WR4(sc, PMC_GPU_RG_CNTRL, 0); in tegra_powergate_remove_clamping()
235 return (0); in tegra_powergate_remove_clamping()
239 if ((reg & PMC_PWRGATE_STATUS_PARTID(id)) == 0) in tegra_powergate_remove_clamping()
250 for (i = 100; i > 0; i--) { in tegra_powergate_remove_clamping()
252 if ((reg & PMC_REMOVE_CLAMPING_CMD_PARTID(swid)) == 0) in tegra_powergate_remove_clamping()
256 if (i <= 0) in tegra_powergate_remove_clamping()
260 if ((reg & PMC_CLAMP_STATUS_PARTID(id)) != 0) in tegra_powergate_remove_clamping()
263 return (0); in tegra_powergate_remove_clamping()
275 return ((reg & PMC_PWRGATE_STATUS_PARTID(id)) ? 1 : 0); in tegra_powergate_is_powered()
287 if (rv != 0) { in tegra_powergate_power_on()
292 for (i = 100; i > 0; i--) { in tegra_powergate_power_on()
297 if (i <= 0) in tegra_powergate_power_on()
311 rv = tegra124_pmc_set_powergate(sc, id, 0); in tegra_powergate_power_off()
312 if (rv != 0) { in tegra_powergate_power_off()
316 for (i = 100; i > 0; i--) { in tegra_powergate_power_off()
321 if (i <= 0) in tegra_powergate_power_off()
337 if (rv != 0) { in tegra_powergate_sequence_power_up()
343 if (rv != 0) { in tegra_powergate_sequence_power_up()
349 if (rv != 0) { in tegra_powergate_sequence_power_up()
355 if (rv != 0) { in tegra_powergate_sequence_power_up()
362 if (rv != 0) { in tegra_powergate_sequence_power_up()
367 if (rv != 0) { in tegra_powergate_sequence_power_up()
371 return 0; in tegra_powergate_sequence_power_up()
389 if (rv > 0) { in tegra124_pmc_parse_fdt()
391 case 0: in tegra124_pmc_parse_fdt()
410 if (rv > 0) { in tegra124_pmc_parse_fdt()
416 if (rv > 0) { in tegra124_pmc_parse_fdt()
424 sc->core_osc_time = tmparr[0]; in tegra124_pmc_parse_fdt()
430 if (rv > 0) { in tegra124_pmc_parse_fdt()
446 sc->lp0_vec_phys = tmparr[0]; in tegra124_pmc_parse_fdt()
452 return 0; in tegra124_pmc_parse_fdt()
490 if (rv != 0) { in tegra124_pmc_attach()
495 rv = clk_get_by_ofw_name(sc->dev, 0, "pclk", &sc->clk); in tegra124_pmc_attach()
496 if (rv != 0) { in tegra124_pmc_attach()
501 rid = 0; in tegra124_pmc_attach()
544 return (0); in tegra124_pmc_attach()