1 /*-
2  * Copyright (C) 2008-2009 Semihalf, Michal Hajduk
35  * Note that the hardware is capable of running as both a master and a slave.
36  * This driver currently implements only master-mode operations.
38  * This driver supports multi-master i2c buses, by detecting bus arbitration
41  * transfer cycles resulting in arbitration loss in mid-transfer.  The caller
42  * must handle retries in a way that makes sense for the slave being addressed.
81 #define I2C_ADDR_REG		0x00 /* I2C slave address register */
89 #define I2CCR_MSTA		(1 << 5) /* Master/slave mode */
90 #define I2CCR_MTX		(1 << 4) /* Transmit/receive mode */
95 #define I2CSR_MASS		(1 << 6) /* Addressed as a slave */
98 #define I2CSR_SRW		(1 << 2) /* Slave read/write */
133 	{"fsl,imx21-i2c",  1},
134 	{"fsl,imx6q-i2c",  1},
135 	{"fsl,imx-i2c",	   1},
149 	u_int			slave;  member
156     if ((lvl) <= (sc)->debug) \
157         device_printf((sc)->dev, fmt, ##args)
160     if ((lvl) <= (sc)->debug) \
219 	bus_write_1(sc->res, off, val);  in i2c_write_reg()
226 	return (bus_read_1(sc->res, off));  in i2c_read_reg()
239 /* Wait for bus to become busy or not-busy. */
246 	while (retry --) {  in wait_for_busbusy()
265 	 * to do clock-stretching so the actual transfer time can be larger, but  in wait_for_xfer()
269 	pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0);  in wait_for_xfer()
272 	while (retry --) {  in wait_for_xfer()
290  *  - Clear master mode (MSTA and MTX).
291  *  - Wait for the bus to become free or for a timeout to happen.
292  *  - Disable the controller.
312 	gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active);  in i2c_recover_getsda()
320 	gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value);  in i2c_recover_setsda()
328 	gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active);  in i2c_recover_getscl()
337 	gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value);  in i2c_recover_setscl()
347 	 * If we have gpio pinmux config, reconfigure the pins to gpio mode,  in i2c_recover_bus()
350 	 * mode (idx 0).  in i2c_recover_bus()
352 	if (sc->rb_pinctl_idx == 0)  in i2c_recover_bus()
355 	fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx);  in i2c_recover_bus()
364 	fdt_pinctrl_configure(sc->dev, 0);  in i2c_recover_bus()
376 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in i2c_probe()
393 	sc->dev = dev;  in i2c_attach()
394 	sc->rid = 0;  in i2c_attach()
397 	if (clk_get_by_ofw_index(sc->dev, 0, 0, &sc->ipgclk) != 0) {  in i2c_attach()
402 	err = clk_enable(sc->ipgclk);  in i2c_attach()
404 		device_printf(sc->dev, "could not enable ipg clock\n");  in i2c_attach()
409 	sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,  in i2c_attach()
411 	if (sc->res == NULL) {  in i2c_attach()
416 	sc->iicbus = device_add_child(dev, "iicbus", DEVICE_UNIT_ANY);  in i2c_attach()
417 	if (sc->iicbus == NULL) {  in i2c_attach()
422 	/* Set up debug-enable sysctl. */  in i2c_attach()
423 	SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),   in i2c_attach()
424 	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),  in i2c_attach()
425 	    OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0,  in i2c_attach()
433 	node = ofw_bus_get_node(sc->dev);  in i2c_attach()
435 	err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios",  in i2c_attach()
436 	    &sc->rb_sclpin);  in i2c_attach()
439 	err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios",  in i2c_attach()
440 	    &sc->rb_sdapin);  in i2c_attach()
449 	gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT);  in i2c_attach()
450 	gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT);  in i2c_attach()
451 	gpio_pin_set_active(sc->rb_sclpin, true);  in i2c_attach()
452 	gpio_pin_set_active(sc->rb_sdapin, true);  in i2c_attach()
457 	 * default pinctrl-0.  If sc->rb_pinctl_idx is non-zero, the reset code  in i2c_attach()
460 	err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx);  in i2c_attach()
462 		snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx);  in i2c_attach()
463 		if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr))  in i2c_attach()
464 			sc->rb_pinctl_idx = cfgidx;  in i2c_attach()
485 	error = clk_disable(sc->ipgclk);  in i2c_detach()
487 		device_printf(sc->dev, "could not disable ipg clock\n");  in i2c_detach()
492 	if ((error = bus_generic_detach(sc->dev)) != 0) {  in i2c_detach()
493 		device_printf(sc->dev, "cannot detach child devices\n");  in i2c_detach()
497 	if (sc->iicbus != NULL)  in i2c_detach()
498 		device_delete_child(dev, sc->iicbus);  in i2c_detach()
500 	/* Release bus-recover pins; gpio_pin_release() handles NULL args. */  in i2c_detach()
501 	gpio_pin_release(sc->rb_sclpin);  in i2c_detach()
502 	gpio_pin_release(sc->rb_sdapin);  in i2c_detach()
504 	if (sc->res != NULL)  in i2c_detach()
505 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res);  in i2c_detach()
511 i2c_repeated_start(device_t dev, u_char slave, int timeout)  in i2c_repeated_start()  argument
524 	 * before writing slave address, wait for ack after write.  in i2c_repeated_start()
529 	i2c_write_reg(sc, I2C_DATA_REG, slave);  in i2c_repeated_start()
530 	sc->slave = slave;  in i2c_repeated_start()
531 	DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->slave);  in i2c_repeated_start()
537 i2c_start_ll(device_t dev, u_char slave, int timeout)  in i2c_start_ll()  argument
553 	i2c_write_reg(sc, I2C_DATA_REG, slave);  in i2c_start_ll()
554 	sc->slave = slave;  in i2c_start_ll()
555 	DEVICE_DEBUGF(sc, 2, "start  0x%02x\n", sc->slave);  in i2c_start_ll()
561 i2c_start(device_t dev, u_char slave, int timeout)  in i2c_start()  argument
569 	 * Invoke the low-level code to put the bus into master mode and address  in i2c_start()
570 	 * the given slave.  If that fails, idle the controller and attempt a  in i2c_start()
572 	 * addressing the slave is the only operation that a low-level driver  in i2c_start()
574 	 * more about the slave device.  in i2c_start()
576 	if ((error = i2c_start_ll(dev, slave, timeout)) != 0) {  in i2c_start()
580 		error = i2c_start_ll(dev, slave, timeout);  in i2c_start()
595 	DEVICE_DEBUGF(sc, 2, "stop   0x%02x\n", sc->slave);  in i2c_stop()
618 	err = clk_get_freq(sc->ipgclk, &freq);  in i2c_reset()
620 		device_printf(sc->dev, "cannot get frequency\n");  in i2c_reset()
627 	busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);  in i2c_reset()
637 	 * pause() while waiting for transfer-complete.  With a 66MHz IPG clock  in i2c_reset()
642 	sc->byte_time_sbt = SBT_1US * (9000000 / busfreq);  in i2c_reset()
653 	 * isn't hung, this a fairly fast no-op.  in i2c_reset()
667 	DEVICE_DEBUGF(sc, 1, "read   0x%02x len %d: ", sc->slave, len);  in i2c_read()
687 			if (*read == len - 2) {  in i2c_read()
691 			} else if (*read == len - 1) {  in i2c_read()
718 	DEVICE_DEBUGF(sc, 1, "write  0x%02x len %d: ", sc->slave, len);  in i2c_write()