Lines Matching +full:tx +full:- +full:delay +full:- +full:ps
1 /*-
71 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
72 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
74 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
75 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
76 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
77 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
86 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
87 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1))
88 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1))
122 /* Burst length of RX and TX DMA transfers */
126 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */
134 /* Request a TX interrupt every <n> descriptors */
149 { "allwinner,sun8i-a83t-emac", EMAC_A83T },
150 { "allwinner,sun8i-h3-emac", EMAC_H3 },
151 { "allwinner,sun50i-a64-emac", EMAC_A64 },
203 struct awg_txring tx; member
211 { -1, 0 }
240 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | in awg_miibus_readreg()
244 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { in awg_miibus_readreg()
249 DELAY(10); in awg_miibus_readreg()
269 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | in awg_miibus_writereg()
273 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { in awg_miibus_writereg()
276 DELAY(10); in awg_miibus_writereg()
297 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0) in awg_miibus_statchg()
299 mii = device_get_softc(sc->miibus); in awg_miibus_statchg()
301 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == in awg_miibus_statchg()
303 switch (IFM_SUBTYPE(mii->mii_media_active)) { in awg_miibus_statchg()
308 sc->link = 1; in awg_miibus_statchg()
311 sc->link = 0; in awg_miibus_statchg()
315 sc->link = 0; in awg_miibus_statchg()
317 if (sc->link == 0) in awg_miibus_statchg()
323 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || in awg_miibus_statchg()
324 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) in awg_miibus_statchg()
326 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) in awg_miibus_statchg()
331 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) in awg_miibus_statchg()
338 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) in awg_miibus_statchg()
344 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) in awg_miibus_statchg()
346 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) in awg_miibus_statchg()
362 mii = device_get_softc(sc->miibus); in awg_media_status()
366 ifmr->ifm_active = mii->mii_media_active; in awg_media_status()
367 ifmr->ifm_status = mii->mii_media_status; in awg_media_status()
379 mii = device_get_softc(sc->miibus); in awg_media_change()
392 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */
427 ifp = sc->ifp; in awg_setup_rxfilter()
472 uint32_t tx, rx; in awg_enable_mac() local
476 tx = RD4(sc, EMAC_TX_CTL_0); in awg_enable_mac()
479 tx |= TX_EN; in awg_enable_mac()
482 tx &= ~TX_EN; in awg_enable_mac()
486 WR4(sc, EMAC_TX_CTL_0, tx); in awg_enable_mac()
557 if ((if_getcapenable(sc->ifp) & IFCAP_POLLING) == 0) in awg_init_dma()
581 /* Stop transmit DMA and flush data in the TX FIFO */ in awg_stop_dma()
609 cur = first = sc->tx.cur; in awg_encap()
610 map = sc->tx.buf_map[first].map; in awg_encap()
613 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, segs, in awg_encap()
618 device_printf(sc->dev, "awg_encap: m_collapse failed\n"); in awg_encap()
624 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, in awg_encap()
632 device_printf(sc->dev, "awg_encap: bus_dmamap_load_mbuf_sg failed\n"); in awg_encap()
641 if (sc->tx.queued + nsegs > TX_DESC_COUNT) { in awg_encap()
642 bus_dmamap_unload(sc->tx.buf_tag, map); in awg_encap()
646 bus_dmamap_sync(sc->tx.buf_tag, map, BUS_DMASYNC_PREWRITE); in awg_encap()
650 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) { in awg_encap()
651 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0) in awg_encap()
659 sc->tx.segs++; in awg_encap()
660 if (i == nsegs - 1) { in awg_encap()
663 * Can only request TX completion in awg_encap()
666 if (sc->tx.segs >= awg_tx_interval) { in awg_encap()
667 sc->tx.segs = 0; in awg_encap()
672 sc->tx.desc_ring[cur].addr = htole32((uint32_t)segs[i].ds_addr); in awg_encap()
673 sc->tx.desc_ring[cur].size = htole32(flags | segs[i].ds_len); in awg_encap()
674 sc->tx.desc_ring[cur].status = htole32(status); in awg_encap()
683 ++sc->tx.queued; in awg_encap()
687 sc->tx.cur = cur; in awg_encap()
690 last = TX_SKIP(cur, TX_DESC_COUNT - 1); in awg_encap()
691 sc->tx.buf_map[first].map = sc->tx.buf_map[last].map; in awg_encap()
692 sc->tx.buf_map[last].map = map; in awg_encap()
693 sc->tx.buf_map[last].mbuf = m; in awg_encap()
699 sc->tx.desc_ring[first].status = htole32(TX_DESC_CTL); in awg_encap()
709 --sc->tx.queued; in awg_clean_txbuf()
711 bmap = &sc->tx.buf_map[index]; in awg_clean_txbuf()
712 if (bmap->mbuf != NULL) { in awg_clean_txbuf()
713 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, in awg_clean_txbuf()
715 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); in awg_clean_txbuf()
716 m_freem(bmap->mbuf); in awg_clean_txbuf()
717 bmap->mbuf = NULL; in awg_clean_txbuf()
727 size = MCLBYTES - 1; in awg_setup_rxdesc()
729 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); in awg_setup_rxdesc()
730 sc->rx.desc_ring[index].size = htole32(size); in awg_setup_rxdesc()
731 sc->rx.desc_ring[index].status = htole32(status); in awg_setup_rxdesc()
738 sc->rx.desc_ring[index].status = htole32(RX_DESC_CTL); in awg_reuse_rxdesc()
753 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; in awg_newbuf_rx()
756 if (bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, sc->rx.buf_spare_map, in awg_newbuf_rx()
762 if (sc->rx.buf_map[index].mbuf != NULL) { in awg_newbuf_rx()
763 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, in awg_newbuf_rx()
765 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); in awg_newbuf_rx()
767 map = sc->rx.buf_map[index].map; in awg_newbuf_rx()
768 sc->rx.buf_map[index].map = sc->rx.buf_spare_map; in awg_newbuf_rx()
769 sc->rx.buf_spare_map = map; in awg_newbuf_rx()
770 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, in awg_newbuf_rx()
773 sc->rx.buf_map[index].mbuf = m; in awg_newbuf_rx()
795 /* Setup TX ring */ in awg_setup_dma()
806 &sc->tx.desc_tag); in awg_setup_dma()
808 device_printf(dev, "cannot create TX descriptor ring tag\n"); in awg_setup_dma()
812 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring, in awg_setup_dma()
813 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map); in awg_setup_dma()
815 device_printf(dev, "cannot allocate TX descriptor ring\n"); in awg_setup_dma()
819 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map, in awg_setup_dma()
820 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb, in awg_setup_dma()
821 &sc->tx.desc_ring_paddr, 0); in awg_setup_dma()
823 device_printf(dev, "cannot load TX descriptor ring\n"); in awg_setup_dma()
828 sc->tx.desc_ring[i].next = in awg_setup_dma()
829 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); in awg_setup_dma()
841 &sc->tx.buf_tag); in awg_setup_dma()
843 device_printf(dev, "cannot create TX buffer tag\n"); in awg_setup_dma()
847 sc->tx.queued = 0; in awg_setup_dma()
849 error = bus_dmamap_create(sc->tx.buf_tag, 0, in awg_setup_dma()
850 &sc->tx.buf_map[i].map); in awg_setup_dma()
852 device_printf(dev, "cannot create TX buffer map\n"); in awg_setup_dma()
868 &sc->rx.desc_tag); in awg_setup_dma()
874 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring, in awg_setup_dma()
875 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map); in awg_setup_dma()
881 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map, in awg_setup_dma()
882 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb, in awg_setup_dma()
883 &sc->rx.desc_ring_paddr, 0); in awg_setup_dma()
899 &sc->rx.buf_tag); in awg_setup_dma()
905 error = bus_dmamap_create(sc->rx.buf_tag, 0, &sc->rx.buf_spare_map); in awg_setup_dma()
913 sc->rx.desc_ring[i].next = in awg_setup_dma()
914 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(i))); in awg_setup_dma()
916 error = bus_dmamap_create(sc->rx.buf_tag, 0, in awg_setup_dma()
917 &sc->rx.buf_map[i].map); in awg_setup_dma()
922 sc->rx.buf_map[i].mbuf = NULL; in awg_setup_dma()
929 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, in awg_setup_dma()
933 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); in awg_setup_dma()
934 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); in awg_setup_dma()
946 /* Start and run TX DMA */ in awg_dma_start_tx()
964 if (!sc->link) in awg_start_locked()
967 ifp = sc->ifp; in awg_start_locked()
990 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, in awg_start_locked()
1015 mii = device_get_softc(sc->miibus); in awg_init_locked()
1016 ifp = sc->ifp; in awg_init_locked()
1031 callout_reset(&sc->stat_ch, hz, awg_tick, sc); in awg_init_locked()
1055 ifp = sc->ifp; in awg_stop()
1057 callout_stop(&sc->stat_ch); in awg_stop()
1062 sc->link = 0; in awg_stop()
1068 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { in awg_stop()
1069 val = le32toh(sc->tx.desc_ring[i].status); in awg_stop()
1074 sc->tx.next = i; in awg_stop()
1075 for (; sc->tx.queued > 0; i = TX_NEXT(i)) { in awg_stop()
1076 sc->tx.desc_ring[i].status = 0; in awg_stop()
1079 sc->tx.cur = sc->tx.next; in awg_stop()
1080 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, in awg_stop()
1084 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, in awg_stop()
1087 for (i = sc->rx.cur; ; i = RX_NEXT(i)) { in awg_stop()
1088 val = le32toh(sc->rx.desc_ring[i].status); in awg_stop()
1093 sc->rx.cur = i; in awg_stop()
1094 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, in awg_stop()
1109 mii = device_get_softc(sc->miibus); in awg_ioctl()
1118 flags = if_getflags(ifp) ^ sc->if_flags; in awg_ioctl()
1127 sc->if_flags = if_getflags(ifp); in awg_ioctl()
1140 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); in awg_ioctl()
1143 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); in awg_ioctl()
1146 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { in awg_ioctl()
1194 ifp = sc->ifp; in awg_rxintr()
1199 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, in awg_rxintr()
1202 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { in awg_rxintr()
1203 status = le32toh(sc->rx.desc_ring[index].status); in awg_rxintr()
1216 m = sc->rx.buf_map[index].mbuf; in awg_rxintr()
1225 m->m_pkthdr.rcvif = ifp; in awg_rxintr()
1226 m->m_pkthdr.len = len; in awg_rxintr()
1227 m->m_len = len; in awg_rxintr()
1232 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; in awg_rxintr()
1234 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; in awg_rxintr()
1236 m->m_pkthdr.csum_flags |= in awg_rxintr()
1238 m->m_pkthdr.csum_data = 0xffff; in awg_rxintr()
1242 m->m_nextpkt = NULL; in awg_rxintr()
1246 mt->m_nextpkt = m; in awg_rxintr()
1260 if (index != sc->rx.cur) { in awg_rxintr()
1261 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, in awg_rxintr()
1271 sc->rx.cur = index; in awg_rxintr()
1286 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, in awg_txeof()
1289 ifp = sc->ifp; in awg_txeof()
1292 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { in awg_txeof()
1293 desc = &sc->tx.desc_ring[i]; in awg_txeof()
1294 status = le32toh(desc->status); in awg_txeof()
1297 size = le32toh(desc->size); in awg_txeof()
1309 sc->tx.next = i; in awg_txeof()
1333 if (!if_sendq_empty(sc->ifp)) in awg_intr()
1384 if (sc->syscon != NULL) in syscon_read_emac_clk_reg()
1385 return (SYSCON_READ_4(sc->syscon, EMAC_CLK_REG)); in syscon_read_emac_clk_reg()
1386 else if (sc->res[_RES_SYSCON] != NULL) in syscon_read_emac_clk_reg()
1387 return (bus_read_4(sc->res[_RES_SYSCON], 0)); in syscon_read_emac_clk_reg()
1398 if (sc->syscon != NULL) in syscon_write_emac_clk_reg()
1399 SYSCON_WRITE_4(sc->syscon, EMAC_CLK_REG, val); in syscon_write_emac_clk_reg()
1400 else if (sc->res[_RES_SYSCON] != NULL) in syscon_write_emac_clk_reg()
1401 bus_write_4(sc->res[_RES_SYSCON], 0, val); in syscon_write_emac_clk_reg()
1415 if (OF_getencprop(node, "phy-handle", (void *)&phy_handle, in awg_get_phy_node()
1429 if (OF_hasprop(node, "allwinner,use-internal-phy")) in awg_has_internal_phy()
1434 "allwinner,sun8i-h3-mdio-internal") != 0); in awg_has_internal_phy()
1441 uint32_t delay; in awg_parse_delay() local
1448 if (OF_getencprop(node, "tx-delay", &delay, sizeof(delay)) >= 0) in awg_parse_delay()
1449 *tx_delay = delay; in awg_parse_delay()
1450 else if (OF_getencprop(node, "allwinner,tx-delay-ps", &delay, in awg_parse_delay()
1451 sizeof(delay)) >= 0) { in awg_parse_delay()
1452 if ((delay % 100) != 0) { in awg_parse_delay()
1453 device_printf(dev, "tx-delay-ps is not a multiple of 100\n"); in awg_parse_delay()
1456 *tx_delay = delay / 100; in awg_parse_delay()
1459 device_printf(dev, "tx-delay out of range\n"); in awg_parse_delay()
1463 if (OF_getencprop(node, "rx-delay", &delay, sizeof(delay)) >= 0) in awg_parse_delay()
1464 *rx_delay = delay; in awg_parse_delay()
1465 else if (OF_getencprop(node, "allwinner,rx-delay-ps", &delay, in awg_parse_delay()
1466 sizeof(delay)) >= 0) { in awg_parse_delay()
1467 if ((delay % 100) != 0) { in awg_parse_delay()
1468 device_printf(dev, "rx-delay-ps is not within documented domain\n"); in awg_parse_delay()
1471 *rx_delay = delay / 100; in awg_parse_delay()
1474 device_printf(dev, "rx-delay out of range\n"); in awg_parse_delay()
1497 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_type) == 0) in awg_setup_phy()
1500 if (sc->syscon != NULL || sc->res[_RES_SYSCON] != NULL) in awg_setup_phy()
1510 * For the pine64, we get dtb from U-Boot and it still uses the in awg_setup_phy()
1513 * These abstractions can go away once U-Boot dts is up-to-date. in awg_setup_phy()
1525 * Fail attach if we fail to parse either of the delay in awg_setup_phy()
1526 * parameters. If we don't have the proper delay to write to in awg_setup_phy()
1528 * Lack of delay is not an error! in awg_setup_phy()
1541 if (sc->type == EMAC_H3) { in awg_setup_phy()
1546 "allwinner,leds-active-low")) in awg_setup_phy()
1568 /* Get the TX clock */ in awg_setup_phy()
1569 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx); in awg_setup_phy()
1571 device_printf(dev, "cannot get tx clock\n"); in awg_setup_phy()
1575 /* Find the desired parent clock based on phy-mode property */ in awg_setup_phy()
1583 /* Set TX clock parent */ in awg_setup_phy()
1586 device_printf(dev, "cannot set tx clock parent\n"); in awg_setup_phy()
1590 /* Enable TX clock */ in awg_setup_phy()
1593 device_printf(dev, "cannot enable tx clock\n"); in awg_setup_phy()
1623 if (phy_node == 0 && OF_hasprop(node, "phy-handle")) { in awg_setup_extres()
1654 "syscon", &sc->syscon) != 0) { in awg_setup_extres()
1677 /* De-assert reset */ in awg_setup_extres()
1680 device_printf(dev, "cannot de-assert ahb reset\n"); in awg_setup_extres()
1685 * The ephy reset is left de-asserted by U-Boot. Assert it in awg_setup_extres()
1692 device_printf(dev, "cannot de-assert ephy reset\n"); in awg_setup_extres()
1698 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) { in awg_setup_extres()
1714 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; in awg_setup_extres()
1716 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; in awg_setup_extres()
1718 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; in awg_setup_extres()
1720 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; in awg_setup_extres()
1729 (uintmax_t)freq, sc->mdc_div_ratio_m); in awg_setup_extres()
1786 device_printf(dev, " %-20s %08x\n", regs[n].name, in awg_dump_regs()
1803 if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop, in awg_phy_reset()
1807 if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop, in awg_phy_reset()
1815 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1, in awg_phy_reset()
1820 if (OF_hasprop(node, "allwinner,reset-active-low")) in awg_phy_reset()
1828 DELAY(delay_prop[0]); in awg_phy_reset()
1830 DELAY(delay_prop[1]); in awg_phy_reset()
1832 DELAY(delay_prop[2]); in awg_phy_reset()
1854 /* Wait for soft reset bit to self-clear */ in awg_reset()
1855 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { in awg_reset()
1858 DELAY(10); in awg_reset()
1884 ifp = sc->ifp; in awg_tick()
1885 mii = device_get_softc(sc->miibus); in awg_tick()
1892 link = sc->link; in awg_tick()
1894 if (sc->link && !link) in awg_tick()
1897 callout_reset(&sc->stat_ch, hz, awg_tick, sc); in awg_tick()
1910 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in awg_probe()
1925 sc->dev = dev; in awg_attach()
1926 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; in awg_attach()
1928 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) { in awg_attach()
1933 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); in awg_attach()
1934 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0); in awg_attach()
1955 error = bus_setup_intr(dev, sc->res[_RES_IRQ], in awg_attach()
1956 INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih); in awg_attach()
1963 sc->ifp = if_alloc(IFT_ETHER); in awg_attach()
1964 if_setsoftc(sc->ifp, sc); in awg_attach()
1965 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev)); in awg_attach()
1966 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); in awg_attach()
1967 if_setstartfn(sc->ifp, awg_start); in awg_attach()
1968 if_setioctlfn(sc->ifp, awg_ioctl); in awg_attach()
1969 if_setinitfn(sc->ifp, awg_init); in awg_attach()
1970 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1); in awg_attach()
1971 if_setsendqready(sc->ifp); in awg_attach()
1972 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP); in awg_attach()
1973 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM); in awg_attach()
1974 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp)); in awg_attach()
1976 if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0); in awg_attach()
1980 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change, in awg_attach()
1989 ether_ifattach(sc->ifp, eaddr); in awg_attach()