Lines Matching +full:sun5i +full:- +full:a13 +full:- +full:pinctrl
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
210 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_gpio_conf},
213 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_gpio_conf},
216 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_gpio_conf},
219 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_gpio_conf},
222 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_gpio_conf},
225 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_gpio_conf},
228 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_gpio_conf},
231 {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_gpio_conf},
232 {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_gpio_conf},
235 {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_gpio_conf},
236 {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_gpio_conf},
237 {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_gpio_conf},
240 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_gpio_conf},
241 {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_gpio_conf},
244 {"allwinner,sun50i-h6-pinctrl", (uintptr_t)&h6_gpio_conf},
245 {"allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&h6_r_gpio_conf},
289 { -1, 0, 0 }
292 #define AW_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
293 #define AW_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
294 #define AW_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
331 bus_write_4((_sc)->sc_res[AW_GPIO_MEMRES], _off, _val)
333 bus_read_4((_sc)->sc_res[AW_GPIO_MEMRES], _off)
343 if (pin > sc->conf->padconf->npins) in aw_gpio_get_function()
345 bank = sc->conf->padconf->pins[pin].port; in aw_gpio_get_function()
346 pin = sc->conf->padconf->pins[pin].pin; in aw_gpio_get_function()
360 if (sc->conf->padconf->pins[pin].functions[f] == NULL) in aw_gpio_set_function()
366 bank = sc->conf->padconf->pins[pin].port; in aw_gpio_set_function()
367 pin = sc->conf->padconf->pins[pin].pin; in aw_gpio_set_function()
386 bank = sc->conf->padconf->pins[pin].port; in aw_gpio_get_pud()
387 pin = sc->conf->padconf->pins[pin].pin; in aw_gpio_get_pud()
406 bank = sc->conf->padconf->pins[pin].port; in aw_gpio_set_pud()
407 pin = sc->conf->padconf->pins[pin].pin; in aw_gpio_set_pud()
424 bank = sc->conf->padconf->pins[pin].port; in aw_gpio_get_drv()
425 pin = sc->conf->padconf->pins[pin].pin; in aw_gpio_get_drv()
444 bank = sc->conf->padconf->pins[pin].port; in aw_gpio_set_drv()
445 pin = sc->conf->padconf->pins[pin].pin; in aw_gpio_set_drv()
463 if (pin > sc->conf->padconf->npins) in aw_gpio_pin_configure()
490 /* Manage Pull-up/pull-down. */ in aw_gpio_pin_configure()
508 return (sc->sc_busdev); in aw_gpio_get_bus()
518 *maxpin = sc->conf->padconf->npins - 1; in aw_gpio_pin_max()
528 if (pin >= sc->conf->padconf->npins) in aw_gpio_pin_getcaps()
532 if (sc->conf->padconf->pins[pin].eint_func != 0) in aw_gpio_pin_getcaps()
546 if (pin >= sc->conf->padconf->npins) in aw_gpio_pin_getflags()
586 if (pin >= sc->conf->padconf->npins) in aw_gpio_pin_getname()
589 snprintf(name, GPIOMAXNAME - 1, "%s", in aw_gpio_pin_getname()
590 sc->conf->padconf->pins[pin].name); in aw_gpio_pin_getname()
591 name[GPIOMAXNAME - 1] = '\0'; in aw_gpio_pin_getname()
603 if (pin > sc->conf->padconf->npins) in aw_gpio_pin_setflags()
621 if (pin > sc->conf->padconf->npins) in aw_gpio_pin_set_locked()
624 bank = sc->conf->padconf->pins[pin].port; in aw_gpio_pin_set_locked()
625 pin = sc->conf->padconf->pins[pin].pin; in aw_gpio_pin_set_locked()
662 if (pin > sc->conf->padconf->npins) in aw_gpio_pin_get_locked()
666 if (func == sc->conf->padconf->pins[pin].eint_func) { /* "pl_eintX */ in aw_gpio_pin_get_locked()
672 bank = sc->conf->padconf->pins[pin].port; in aw_gpio_pin_get_locked()
673 pin = sc->conf->padconf->pins[pin].pin; in aw_gpio_pin_get_locked()
678 if (func == sc->conf->padconf->pins[pin].eint_func) in aw_gpio_pin_get_locked()
690 (void **)&function) != -1) in aw_gpio_parse_function()
693 (void **)&function) != -1) in aw_gpio_parse_function()
721 if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1) in aw_gpio_parse_bias()
723 if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1) in aw_gpio_parse_bias()
725 if (OF_hasprop(node, "bias-disable")) in aw_gpio_parse_bias()
727 if (OF_hasprop(node, "bias-pull-up")) in aw_gpio_parse_bias()
729 if (OF_hasprop(node, "bias-pull-down")) in aw_gpio_parse_bias()
740 if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1) in aw_gpio_parse_drive_strength()
742 if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1) in aw_gpio_parse_drive_strength()
744 if (OF_getencprop(node, "drive-strength", &drive_str, in aw_gpio_parse_drive_strength()
745 sizeof(drive_str)) != -1) { in aw_gpio_parse_drive_strength()
746 *drive = (drive_str / 10) - 1; in aw_gpio_parse_drive_strength()
775 if (pin > sc->conf->padconf->npins) in aw_gpio_pin_toggle()
778 bank = sc->conf->padconf->pins[pin].port; in aw_gpio_pin_toggle()
779 pin = sc->conf->padconf->pins[pin].pin; in aw_gpio_pin_toggle()
801 if (first_pin > sc->conf->padconf->npins) in aw_gpio_pin_access_32()
808 * (desired); we need to do a read-modify-write on a single register. in aw_gpio_pin_access_32()
810 bank = sc->conf->padconf->pins[first_pin].port; in aw_gpio_pin_access_32()
811 pin = sc->conf->padconf->pins[first_pin].pin; in aw_gpio_pin_access_32()
837 if (first_pin > sc->conf->padconf->npins) in aw_gpio_pin_config_32()
840 if (sc->conf->padconf->pins[first_pin].pin != 0) in aw_gpio_pin_config_32()
868 /* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */ in aw_gpio_map_gpios()
869 for (i = 0; i < sc->conf->padconf->npins; i++) in aw_gpio_map_gpios()
870 if (sc->conf->padconf->pins[i].port == gpios[0] && in aw_gpio_map_gpios()
871 sc->conf->padconf->pins[i].pin == gpios[1]) { in aw_gpio_map_gpios()
875 *flags = gpios[gcells - 1]; in aw_gpio_map_gpios()
885 for (i = 0; i < sc->conf->padconf->npins; i++) in aw_find_pinnum_by_name()
886 if (!strcmp(pinname, sc->conf->padconf->pins[i].name)) in aw_find_pinnum_by_name()
889 return (-1); in aw_find_pinnum_by_name()
898 if (sc->conf->padconf->pins[pin].functions[i] && in aw_find_pin_func()
899 !strcmp(func, sc->conf->padconf->pins[pin].functions[i])) in aw_find_pin_func()
902 return (-1); in aw_find_pin_func()
940 if (pin_num == -1) { in aw_fdt_configure_pins()
945 if (pin_func == -1) { in aw_fdt_configure_pins()
976 nbanks = strlen(sc->conf->banks); in aw_gpio_enable_bank_supply()
978 snprintf(bank_reg_name, sizeof(bank_reg_name), "vcc-p%c-supply", in aw_gpio_enable_bank_supply()
979 sc->conf->banks[i]); in aw_gpio_enable_bank_supply()
981 if (regulator_get_by_ofw_property(sc->sc_dev, 0, bank_reg_name, &vcc_supply) == 0) { in aw_gpio_enable_bank_supply()
983 device_printf(sc->sc_dev, in aw_gpio_enable_bank_supply()
985 sc->conf->banks[i]); in aw_gpio_enable_bank_supply()
987 device_printf(sc->sc_dev, in aw_gpio_enable_bank_supply()
989 sc->conf->banks[i]); in aw_gpio_enable_bank_supply()
1002 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in aw_gpio_probe()
1021 sc->sc_dev = dev; in aw_gpio_attach()
1023 mtx_init(&sc->sc_mtx, "aw gpio", "gpio", MTX_SPIN); in aw_gpio_attach()
1025 if (bus_alloc_resources(dev, aw_gpio_res_spec, sc->sc_res) != 0) { in aw_gpio_attach()
1030 if (bus_setup_intr(dev, sc->sc_res[AW_GPIO_IRQRES], in aw_gpio_attach()
1032 &sc->sc_intrhand)) { in aw_gpio_attach()
1038 gpio = ofw_bus_get_node(sc->sc_dev); in aw_gpio_attach()
1039 if (!OF_hasprop(gpio, "gpio-controller")) in aw_gpio_attach()
1044 sc->conf = (struct aw_gpio_conf *)ofw_bus_search_compatible(dev, in aw_gpio_attach()
1045 compat_data)->ocd_data; in aw_gpio_attach()
1050 device_printf(dev, "cannot de-assert reset\n"); in aw_gpio_attach()
1055 TAILQ_INIT(&sc->clk_list); in aw_gpio_attach()
1067 clkp->clk = clk; in aw_gpio_attach()
1068 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next); in aw_gpio_attach()
1079 sc->sc_busdev = gpiobus_attach_bus(dev); in aw_gpio_attach()
1080 if (sc->sc_busdev == NULL) in aw_gpio_attach()
1084 * Register as a pinctrl device in aw_gpio_attach()
1096 if (sc->sc_irq_res) in aw_gpio_attach()
1097 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); in aw_gpio_attach()
1098 if (sc->sc_mem_res) in aw_gpio_attach()
1099 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); in aw_gpio_attach()
1100 mtx_destroy(&sc->sc_mtx); in aw_gpio_attach()
1103 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { in aw_gpio_attach()
1104 err = clk_disable(clkp->clk); in aw_gpio_attach()
1107 clk_get_name(clkp->clk)); in aw_gpio_attach()
1108 err = clk_release(clkp->clk); in aw_gpio_attach()
1111 clk_get_name(clkp->clk)); in aw_gpio_attach()
1112 TAILQ_REMOVE(&sc->clk_list, clkp, next); in aw_gpio_attach()
1143 for (irq = 0; irq < sc->nirqs; irq++) { in aw_gpio_intr()
1144 if (!sc->gpio_pic_irqsrc[irq].enabled) in aw_gpio_intr()
1147 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_STA(sc->gpio_pic_irqsrc[irq].bank)); in aw_gpio_intr()
1148 if (!(reg & (1 << sc->gpio_pic_irqsrc[irq].intnum))) in aw_gpio_intr()
1151 isrc = &sc->gpio_pic_irqsrc[irq].isrc; in aw_gpio_intr()
1152 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) { in aw_gpio_intr()
1154 aw_gpio_pic_post_filter(sc->sc_dev, isrc); in aw_gpio_intr()
1155 device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq); in aw_gpio_intr()
1173 name = device_get_nameunit(sc->sc_dev); in aw_gpio_register_isrcs()
1175 for (nirqs = 0, pin = 0; pin < sc->conf->padconf->npins; pin++) { in aw_gpio_register_isrcs()
1176 if (sc->conf->padconf->pins[pin].eint_func == 0) in aw_gpio_register_isrcs()
1182 sc->gpio_pic_irqsrc = malloc(sizeof(*sc->gpio_pic_irqsrc) * nirqs, in aw_gpio_register_isrcs()
1184 for (nirqs = 0, pin = 0; pin < sc->conf->padconf->npins; pin++) { in aw_gpio_register_isrcs()
1185 if (sc->conf->padconf->pins[pin].eint_func == 0) in aw_gpio_register_isrcs()
1188 sc->gpio_pic_irqsrc[nirqs].pin = pin; in aw_gpio_register_isrcs()
1189 sc->gpio_pic_irqsrc[nirqs].bank = sc->conf->padconf->pins[pin].eint_bank; in aw_gpio_register_isrcs()
1190 sc->gpio_pic_irqsrc[nirqs].intnum = sc->conf->padconf->pins[pin].eint_num; in aw_gpio_register_isrcs()
1191 sc->gpio_pic_irqsrc[nirqs].intfunc = sc->conf->padconf->pins[pin].eint_func; in aw_gpio_register_isrcs()
1192 sc->gpio_pic_irqsrc[nirqs].irq = nirqs; in aw_gpio_register_isrcs()
1193 sc->gpio_pic_irqsrc[nirqs].mode = GPIO_INTR_CONFORM; in aw_gpio_register_isrcs()
1195 err = intr_isrc_register(&sc->gpio_pic_irqsrc[nirqs].isrc, in aw_gpio_register_isrcs()
1196 sc->sc_dev, 0, "%s,%s", name, in aw_gpio_register_isrcs()
1197 sc->conf->padconf->pins[pin].functions[sc->conf->padconf->pins[pin].eint_func]); in aw_gpio_register_isrcs()
1199 device_printf(sc->sc_dev, "intr_isrs_register failed for irq %d\n", nirqs); in aw_gpio_register_isrcs()
1205 sc->nirqs = nirqs; in aw_gpio_register_isrcs()
1217 irq = ((struct gpio_irqsrc *)isrc)->irq; in aw_gpio_pic_disable_intr_locked()
1218 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank)); in aw_gpio_pic_disable_intr_locked()
1219 reg &= ~(1 << sc->gpio_pic_irqsrc[irq].intnum); in aw_gpio_pic_disable_intr_locked()
1220 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg); in aw_gpio_pic_disable_intr_locked()
1222 sc->gpio_pic_irqsrc[irq].enabled = false; in aw_gpio_pic_disable_intr_locked()
1245 irq = ((struct gpio_irqsrc *)isrc)->irq; in aw_gpio_pic_enable_intr()
1247 reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank)); in aw_gpio_pic_enable_intr()
1248 reg |= 1 << sc->gpio_pic_irqsrc[irq].intnum; in aw_gpio_pic_enable_intr()
1249 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg); in aw_gpio_pic_enable_intr()
1252 sc->gpio_pic_irqsrc[irq].enabled = true; in aw_gpio_pic_enable_intr()
1262 irq = dag->gpio_pin_num; in aw_gpio_pic_map_gpio()
1264 for (pin = 0; pin < sc->nirqs; pin++) in aw_gpio_pic_map_gpio()
1265 if (sc->gpio_pic_irqsrc[pin].pin == irq) in aw_gpio_pic_map_gpio()
1267 if (pin == sc->nirqs) { in aw_gpio_pic_map_gpio()
1268 device_printf(sc->sc_dev, "Invalid interrupt number %u\n", irq); in aw_gpio_pic_map_gpio()
1272 switch (dag->gpio_intr_mode) { in aw_gpio_pic_map_gpio()
1280 device_printf(sc->sc_dev, "Unsupported interrupt mode 0x%8x\n", in aw_gpio_pic_map_gpio()
1281 dag->gpio_intr_mode); in aw_gpio_pic_map_gpio()
1287 *mode = dag->gpio_intr_mode; in aw_gpio_pic_map_gpio()
1301 switch (data->type) { in aw_gpio_pic_map_intr()
1312 *isrcp = &sc->gpio_pic_irqsrc[irq].isrc; in aw_gpio_pic_map_intr()
1329 switch (data->type) { in aw_gpio_pic_setup_intr()
1341 pinidx = (sc->gpio_pic_irqsrc[irq].intnum % 8) * 4; in aw_gpio_pic_setup_intr()
1363 sc->gpio_pic_irqsrc[irq].oldfunc = aw_gpio_get_function(sc, in aw_gpio_pic_setup_intr()
1364 sc->gpio_pic_irqsrc[irq].pin); in aw_gpio_pic_setup_intr()
1365 aw_gpio_set_function(sc, sc->gpio_pic_irqsrc[irq].pin, in aw_gpio_pic_setup_intr()
1366 sc->gpio_pic_irqsrc[irq].intfunc); in aw_gpio_pic_setup_intr()
1370 AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank, in aw_gpio_pic_setup_intr()
1371 sc->gpio_pic_irqsrc[irq].intnum)); in aw_gpio_pic_setup_intr()
1375 AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank, in aw_gpio_pic_setup_intr()
1376 sc->gpio_pic_irqsrc[irq].intnum), in aw_gpio_pic_setup_intr()
1396 aw_gpio_set_function(sc, gi->pin, gi->oldfunc); in aw_gpio_pic_teardown_intr()
1412 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_STA(gi->bank), 1 << gi->intnum); in aw_gpio_pic_post_filter()
1425 AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_STA(gi->bank), 1 << gi->intnum); in aw_gpio_pic_post_ithread()