1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
45 #define	MSI_X86_ADDR_MASK	0xfff00000
46 #define	MSI_X86_ADDR_BASE	0xfee00000
47 #define	MSI_X86_ADDR_RH		0x00000008	/* Redirection Hint */
48 #define	MSI_X86_ADDR_LOG	0x00000004	/* Destination Mode */
65 	return (0);  in lapic_set_intr()
76 		error = 0;  in lapic_set_local_intr()
103 		return (-1);  in lapic_intr_msi()
107 	 * Extract the x86-specific fields from the MSI addr/msg  in lapic_intr_msi()
111 	 * MSI/MSI-X so ignore trigger level in 'msg'.  in lapic_intr_msi()
117 	dest = (addr >> 12) & 0xff;  in lapic_intr_msi()
121 	vec = msg & 0xff;  in lapic_intr_msi()
127 	return (0);  in lapic_intr_msi()
133 	return (msr >= 0x800 && msr <= 0xBFF);  in x2apic_msr()
140 	return ((msr - 0x800) << 4);  in x2apic_msr_to_regoff()
161 		error = 0;  in lapic_rdmsr()
164 		error = vlapic_read(vlapic, 0, offset, rval, retu);  in lapic_rdmsr()
183 		error = vlapic_write(vlapic, 0, offset, val, retu);  in lapic_wrmsr()
190 lapic_mmio_write(struct vcpu *vcpu, uint64_t gpa, uint64_t wval, int size,  in lapic_mmio_write()  argument
197 	off = gpa - DEFAULT_APIC_BASE;  in lapic_mmio_write()
201 	 * aligned on a 16-byte boundary.  in lapic_mmio_write()
203 	if (size != 4 || off & 0xf)  in lapic_mmio_write()
212 lapic_mmio_read(struct vcpu *vcpu, uint64_t gpa, uint64_t *rval, int size,  in lapic_mmio_read()  argument
219 	off = gpa - DEFAULT_APIC_BASE;  in lapic_mmio_read()
223 	 * 16-byte boundary.  They are also suggested to be 4 bytes  in lapic_mmio_read()
227 	if (off & 0xf)  in lapic_mmio_read()