Lines Matching +full:high +full:- +full:bandwidth

7 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
14 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
18 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4…
21 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
25 …"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY …
28 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
33 …"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUE…
36 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
40 …- ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED…
43 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
50 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
57 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
84 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
90 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
96 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
102         "BriefDescription": "The ratio of Executed- by Issued-Uops",
106 …iption": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions…
109         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
115         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
133 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
139 …   "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
206 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in co…
210 … Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overesti…
213 …BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
219         "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
225         "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
231         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
293 …"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #…
310         "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
329         "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
335         "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
341         "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
347         "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
353         "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
359         "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
365         "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",