Lines Matching +full:3 +full:at
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 "Counter": "0,1,2,3",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3",
33 "CounterHTOff": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
50 "Counter": "0,1,2,3",
51 "CounterHTOff": "0,1,2,3,4,5,6,7",
59 "Counter": "0,1,2,3",
60 "CounterHTOff": "0,1,2,3,4,5,6,7",
68 "Counter": "0,1,2,3",
69 "CounterHTOff": "0,1,2,3,4,5,6,7",
77 "Counter": "0,1,2,3",
78 "CounterHTOff": "0,1,2,3,4,5,6,7",
86 "Counter": "0,1,2,3",
87 "CounterHTOff": "0,1,2,3,4,5,6,7",
95 "Counter": "0,1,2,3",
96 "CounterHTOff": "0,1,2,3,4,5,6,7",
104 "Counter": "0,1,2,3",
105 "CounterHTOff": "0,1,2,3,4,5,6,7",
113 "Counter": "0,1,2,3",
114 "CounterHTOff": "0,1,2,3,4,5,6,7",
122 "Counter": "0,1,2,3",
123 "CounterHTOff": "0,1,2,3,4,5,6,7",
131 "Counter": "0,1,2,3",
132 "CounterHTOff": "0,1,2,3,4,5,6,7",
135 "PublicDescription": "Branch instructions at retirement.",
140 "Counter": "0,1,2,3",
141 "CounterHTOff": "0,1,2,3",
150 "Counter": "0,1,2,3",
151 "CounterHTOff": "0,1,2,3,4,5,6,7",
161 "Counter": "0,1,2,3",
162 "CounterHTOff": "0,1,2,3,4,5,6,7",
171 "Counter": "0,1,2,3",
172 "CounterHTOff": "0,1,2,3,4,5,6,7",
180 …riefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
181 "Counter": "0,1,2,3",
182 "CounterHTOff": "0,1,2,3,4,5,6,7",
191 "Counter": "0,1,2,3",
192 "CounterHTOff": "0,1,2,3,4,5,6,7",
202 "Counter": "0,1,2,3",
203 "CounterHTOff": "0,1,2,3,4,5,6,7",
213 "Counter": "0,1,2,3",
214 "CounterHTOff": "0,1,2,3,4,5,6,7",
223 "Counter": "0,1,2,3",
224 "CounterHTOff": "0,1,2,3,4,5,6,7",
233 "Counter": "0,1,2,3",
234 "CounterHTOff": "0,1,2,3,4,5,6,7",
242 "Counter": "0,1,2,3",
243 "CounterHTOff": "0,1,2,3,4,5,6,7",
251 "Counter": "0,1,2,3",
252 "CounterHTOff": "0,1,2,3,4,5,6,7",
260 "Counter": "0,1,2,3",
261 "CounterHTOff": "0,1,2,3,4,5,6,7",
269 "Counter": "0,1,2,3",
270 "CounterHTOff": "0,1,2,3,4,5,6,7",
278 "Counter": "0,1,2,3",
279 "CounterHTOff": "0,1,2,3,4,5,6,7",
287 "Counter": "0,1,2,3",
288 "CounterHTOff": "0,1,2,3,4,5,6,7",
296 "Counter": "0,1,2,3",
297 "CounterHTOff": "0,1,2,3,4,5,6,7",
300 "PublicDescription": "Mispredicted branch instructions at retirement.",
305 "Counter": "0,1,2,3",
306 "CounterHTOff": "0,1,2,3",
316 "Counter": "0,1,2,3",
317 "CounterHTOff": "0,1,2,3,4,5,6,7",
326 "Counter": "0,1,2,3",
327 "CounterHTOff": "0,1,2,3,4,5,6,7",
337 "Counter": "0,1,2,3",
338 "CounterHTOff": "0,1,2,3",
345 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
346 "Counter": "0,1,2,3",
347 "CounterHTOff": "0,1,2,3,4,5,6,7",
350 "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.",
356 …riefDescription": "Reference cycles when the at least one thread on the physical core is unhalted …
357 "Counter": "0,1,2,3",
358 "CounterHTOff": "0,1,2,3,4,5,6,7",
361 …blicDescription": "Reference cycles when the at least one thread on the physical core is unhalted …
367 "Counter": "0,1,2,3",
368 "CounterHTOff": "0,1,2,3,4,5,6,7",
384 "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
385 "Counter": "0,1,2,3",
386 "CounterHTOff": "0,1,2,3,4,5,6,7",
389 … "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)",
395 …riefDescription": "Reference cycles when the at least one thread on the physical core is unhalted …
396 "Counter": "0,1,2,3",
397 "CounterHTOff": "0,1,2,3,4,5,6,7",
400 …blicDescription": "Reference cycles when the at least one thread on the physical core is unhalted …
415 …"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt stat…
424 "Counter": "0,1,2,3",
425 "CounterHTOff": "0,1,2,3,4,5,6,7",
433 …"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt stat…
434 "Counter": "0,1,2,3",
435 "CounterHTOff": "0,1,2,3,4,5,6,7",
453 "Counter": "0,1,2,3",
454 "CounterHTOff": "0,1,2,3,4,5,6,7",
465 "Counter": "0,1,2,3",
466 "CounterHTOff": "0,1,2,3",
476 "Counter": "0,1,2,3",
477 "CounterHTOff": "0,1,2,3",
498 "Counter": "0,1,2,3",
499 "CounterHTOff": "0,1,2,3",
510 "Counter": "0,1,2,3",
511 "CounterHTOff": "0,1,2,3",
521 "Counter": "0,1,2,3",
522 "CounterHTOff": "0,1,2,3,4,5,6,7",
531 "Counter": "0,1,2,3",
532 "CounterHTOff": "0,1,2,3,4,5,6,7",
551 "Counter": "0,1,2,3",
552 "CounterHTOff": "0,1,2,3,4,5,6,7",
556 "PublicDescription": "Number of instructions at retirement.",
573 "Counter": "0,1,2,3",
574 "CounterHTOff": "0,1,2,3,4,5,6,7",
583 "Counter": "0,1,2,3",
584 "CounterHTOff": "0,1,2,3,4,5,6,7",
595 "Counter": "0,1,2,3",
596 "CounterHTOff": "0,1,2,3,4,5,6,7",
606 "Counter": "0,1,2,3",
607 "CounterHTOff": "0,1,2,3,4,5,6,7",
616 "Counter": "0,1,2,3",
617 "CounterHTOff": "0,1,2,3,4,5,6,7",
626 "Counter": "0,1,2,3",
627 "CounterHTOff": "0,1,2,3,4,5,6,7",
636 "Counter": "0,1,2,3",
637 "CounterHTOff": "0,1,2,3,4,5,6,7",
646 "Counter": "0,1,2,3",
647 "CounterHTOff": "0,1,2,3,4,5,6,7",
656 "Counter": "0,1,2,3",
657 "CounterHTOff": "0,1,2,3,4,5,6,7",
666 "Counter": "0,1,2,3",
667 "CounterHTOff": "0,1,2,3,4,5,6,7",
676 "Counter": "0,1,2,3",
677 "CounterHTOff": "0,1,2,3,4,5,6,7",
686 "Counter": "0,1,2,3",
687 "CounterHTOff": "0,1,2,3,4,5,6,7",
697 "Counter": "0,1,2,3",
698 "CounterHTOff": "0,1,2,3,4,5,6,7",
706 "Counter": "0,1,2,3",
707 "CounterHTOff": "0,1,2,3,4,5,6,7",
715 "Counter": "0,1,2,3",
716 "CounterHTOff": "0,1,2,3,4,5,6,7",
725 "Counter": "0,1,2,3",
726 "CounterHTOff": "0,1,2,3,4,5,6,7",
735 "Counter": "0,1,2,3",
736 "CounterHTOff": "0,1,2,3,4,5,6,7",
745 "Counter": "0,1,2,3",
746 "CounterHTOff": "0,1,2,3,4,5,6,7",
755 "Counter": "0,1,2,3",
756 "CounterHTOff": "0,1,2,3,4,5,6,7",
766 "Counter": "0,1,2,3",
767 "CounterHTOff": "0,1,2,3,4,5,6,7",
775 "Counter": "0,1,2,3",
776 "CounterHTOff": "0,1,2,3,4,5,6,7",
784 "Counter": "0,1,2,3",
785 "CounterHTOff": "0,1,2,3,4,5,6,7",
794 "Counter": "0,1,2,3",
795 "CounterHTOff": "0,1,2,3,4,5,6,7",
804 "Counter": "0,1,2,3",
805 "CounterHTOff": "0,1,2,3,4,5,6,7",
814 "Counter": "0,1,2,3",
815 "CounterHTOff": "0,1,2,3,4,5,6,7",
826 "Counter": "0,1,2,3",
827 "CounterHTOff": "0,1,2,3,4,5,6,7",
835 "Counter": "0,1,2,3",
836 "CounterHTOff": "0,1,2,3,4,5,6,7",
844 "Counter": "0,1,2,3",
845 "CounterHTOff": "0,1,2,3,4,5,6,7",
852 "BriefDescription": "Cycles per thread when uops are executed in port 3.",
853 "Counter": "0,1,2,3",
854 "CounterHTOff": "0,1,2,3,4,5,6,7",
862 "Counter": "0,1,2,3",
863 "CounterHTOff": "0,1,2,3,4,5,6,7",
871 "Counter": "0,1,2,3",
872 "CounterHTOff": "0,1,2,3,4,5,6,7",
880 "Counter": "0,1,2,3",
881 "CounterHTOff": "0,1,2,3,4,5,6,7",
889 "Counter": "0,1,2,3",
890 "CounterHTOff": "0,1,2,3,4,5,6,7",
898 "Counter": "0,1,2,3",
899 "CounterHTOff": "0,1,2,3,4,5,6,7",
908 … "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
909 "Counter": "0,1,2,3",
910 "CounterHTOff": "0,1,2,3,4,5,6,7",
919 … "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
920 "Counter": "0,1,2,3",
921 "CounterHTOff": "0,1,2,3,4,5,6,7",
930 … "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
931 "Counter": "0,1,2,3",
932 "CounterHTOff": "0,1,2,3,4,5,6,7",
933 "CounterMask": "3",
941 … "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
942 "Counter": "0,1,2,3",
943 "CounterHTOff": "0,1,2,3,4,5,6,7",
953 "Counter": "0,1,2,3",
954 "CounterHTOff": "0,1,2,3,4,5,6,7",
963 "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
964 "Counter": "0,1,2,3",
965 "CounterHTOff": "0,1,2,3",
970 …"PublicDescription": "This events counts the cycles where at least one uop was executed. It is cou…
975 "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
976 "Counter": "0,1,2,3",
977 "CounterHTOff": "0,1,2,3",
982 …"PublicDescription": "This events counts the cycles where at least two uop were executed. It is co…
987 "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
988 "Counter": "0,1,2,3",
989 "CounterHTOff": "0,1,2,3",
990 "CounterMask": "3",
994 …"PublicDescription": "This events counts the cycles where at least three uop were executed. It is …
999 "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
1000 "Counter": "0,1,2,3",
1001 "CounterHTOff": "0,1,2,3",
1011 "Counter": "0,1,2,3",
1012 "CounterHTOff": "0,1,2,3",
1023 "Counter": "0,1,2,3",
1024 "CounterHTOff": "0,1,2,3,4,5,6,7",
1034 "Counter": "0,1,2,3",
1035 "CounterHTOff": "0,1,2,3,4,5,6,7",
1044 "Counter": "0,1,2,3",
1045 "CounterHTOff": "0,1,2,3,4,5,6,7",
1055 "Counter": "0,1,2,3",
1056 "CounterHTOff": "0,1,2,3,4,5,6,7",
1065 "Counter": "0,1,2,3",
1066 "CounterHTOff": "0,1,2,3,4,5,6,7",
1076 "Counter": "0,1,2,3",
1077 "CounterHTOff": "0,1,2,3,4,5,6,7",
1084 "BriefDescription": "Cycles per thread when uops are executed in port 3",
1085 "Counter": "0,1,2,3",
1086 "CounterHTOff": "0,1,2,3,4,5,6,7",
1089 "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.",
1095 "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
1096 "Counter": "0,1,2,3",
1097 "CounterHTOff": "0,1,2,3,4,5,6,7",
1105 "Counter": "0,1,2,3",
1106 "CounterHTOff": "0,1,2,3,4,5,6,7",
1116 "Counter": "0,1,2,3",
1117 "CounterHTOff": "0,1,2,3,4,5,6,7",
1126 "Counter": "0,1,2,3",
1127 "CounterHTOff": "0,1,2,3,4,5,6,7",
1137 "Counter": "0,1,2,3",
1138 "CounterHTOff": "0,1,2,3,4,5,6,7",
1147 "Counter": "0,1,2,3",
1148 "CounterHTOff": "0,1,2,3,4,5,6,7",
1158 "Counter": "0,1,2,3",
1159 "CounterHTOff": "0,1,2,3,4,5,6,7",
1168 "Counter": "0,1,2,3",
1169 "CounterHTOff": "0,1,2,3,4,5,6,7",
1179 "Counter": "0,1,2,3",
1180 "CounterHTOff": "0,1,2,3,4,5,6,7",
1188 "Counter": "0,1,2,3",
1189 "CounterHTOff": "0,1,2,3,4,5,6,7",
1192 …ed by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage…
1199 "Counter": "0,1,2,3",
1200 "CounterHTOff": "0,1,2,3",
1210 "Counter": "0,1,2,3",
1211 "CounterHTOff": "0,1,2,3,4,5,6,7",
1220 "Counter": "0,1,2,3",
1221 "CounterHTOff": "0,1,2,3,4,5,6,7",
1229 …w LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sour…
1230 "Counter": "0,1,2,3",
1231 "CounterHTOff": "0,1,2,3,4,5,6,7",
1234 …"PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for ex…
1240 "Counter": "0,1,2,3",
1241 "CounterHTOff": "0,1,2,3",
1251 "Counter": "0,1,2,3",
1252 "CounterHTOff": "0,1,2,3,4,5,6,7",
1263 "Counter": "0,1,2,3",
1264 "CounterHTOff": "0,1,2,3",
1274 "Counter": "0,1,2,3",
1275 "CounterHTOff": "0,1,2,3,4,5,6,7",
1285 "Counter": "0,1,2,3",
1286 "CounterHTOff": "0,1,2,3",
1296 "Counter": "0,1,2,3",
1297 "CounterHTOff": "0,1,2,3",