Lines Matching +full:a +full:- +full:h

14 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
89 .Bl -tag -width indent
98 (RFO) requests generated by a write to data cacheline.
114 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
121 and was serviced by another core with a cross core snoop where no modified
125 and was serviced by another core with a cross core snoop where modified
129 by forwarded data following a cross package snoop where no modified
138 Non-DRAM requests that were serviced by IOH.
142 events measured in a cycle is greater than or equal to
145 Configure the PMC to count the number of de-asserted to asserted
147 If specified, the counter will increment only once whenever a
172 .Bl -tag -width indent
174 .Pq Event 03H , Umask 02H
177 .Pq Event 04H , Umask 07H
180 .Pq Event 05H , Umask 02H
183 .Pq Event 06H , Umask 04H
184 Counts number of loads delayed with at-Retirement block code.
191 .Pq Event 06H , Umask 08H
194 .Pq Event 07H , Umask 01H
197 .Pq Event 08H , Umask 01H
198 Counts all load misses that cause a page walk
200 .Pq Event 08H , Umask 02H
203 .Pq Event 08H , Umask 04H
204 Cycles PMH is busy with a page walk due to a load miss in the STLB.
206 .Pq Event 08H , Umask 10H
209 .Pq Event 08H , Umask 20H
213 .Pq Event 0BH , Umask 01H
214 Counts the number of instructions with an architecturally-visible store
218 .Pq Event 0BH , Umask 02H
219 Counts the number of instructions with an architecturally-visible store
223 .Pq Event 0BH , Umask 10H
228 .Pq Event 0CH , Umask 01H
230 The DTLB miss is not counted if the store operation causes a fault.
234 .Pq Event 0EH , Umask 01H
239 .Pq Event 0EH , Umask 01H
245 .Pq Event 0EH , Umask 02H
249 .Pq Event 0FH , Umask 02H
253 .Pq Event 0FH , Umask 08H
257 .Pq Event 0FH , Umask 10H
258 Load instructions retired with a data source of local DRAM or locally homed
261 .Pq Event 0FH , Umask 20H
262 Load instructions retired remote DRAM and remote home-remote cache HITM
265 .Pq Event 0FH , Umask 80H
268 .Pq Event 10H , Umask 01H
274 of a transcendental flow from a separate FADD instruction.
276 .Pq Event 10H , Umask 02H
279 .Pq Event 10H , Umask 04H
282 .Pq Event 10H , Umask 08H
285 .Pq Event 10H , Umask 10H
288 .Pq Event 10H , Umask 20H
291 .Pq Event 10H , Umask 40H
294 .Pq Event 10H , Umask 80H
297 .Pq Event 12H , Umask 01H
300 .Pq Event 12H , Umask 02H
303 .Pq Event 12H , Umask 04H
306 .Pq Event 12H , Umask 08H
309 .Pq Event 12H , Umask 10H
312 .Pq Event 12H , Umask 20H
315 .Pq Event 12H , Umask 40H
318 .Pq Event 13H , Umask 01H
322 .Pq Event 13H , Umask 02H
325 from the one-cycle delayed staging latch before it is written into the LB.
327 .Pq Event 13H , Umask 04H
331 .Pq Event 13H , Umask 07H
334 .Pq Event 14H , Umask 01H
342 .Pq Event 14H , Umask 02H
348 .Pq Event 17H , Umask 01H
352 .Pq Event 18H , Umask 01H
356 .Pq Event 19H , Umask 01H
359 .Pq Event 1EH , Umask 01H
367 decode enough instructions per cycle to sustain the 4-wide pipeline.
372 .Pq Event 20H , Umask 01H
375 .Pq Event 24H , Umask 01H
381 .Pq Event 24H , Umask 02H
385 .Pq Event 24H , Umask 03H
389 .Pq Event 24H , Umask 04H
396 .Pq Event 24H , Umask 08H
401 .Pq Event 24H , Umask 0CH
406 .Pq Event 24H , Umask 10H
411 .Pq Event 24H , Umask 20H
416 .Pq Event 24H , Umask 30H
421 .Pq Event 24H , Umask 40H
424 .Pq Event 24H , Umask 80H
427 .Pq Event 24H , Umask C0H
430 .Pq Event 24H , Umask AAH
433 .Pq Event 24H , Umask FFH
436 .Pq Event 26H , Umask 01H
438 in the I (invalid) state, i.e. a cache miss.
441 .Pq Event 26H , Umask 02H
447 .Pq Event 26H , Umask 04H
453 .Pq Event 26H , Umask 08H
459 .Pq Event 26H , Umask 0FH
464 .Pq Event 26H , Umask 10H
466 in the I (invalid) state, i.e. a cache miss.
468 .Pq Event 26H , Umask 20H
471 A prefetch RFO will miss on an S state line, while
472 a prefetch read will hit on an S state line.
474 .Pq Event 26H , Umask 40H
478 .Pq Event 26H , Umask 80H
482 .Pq Event 26H , Umask F0H
485 .Pq Event 26H , Umask FFH
488 .Pq Event 27H , Umask 01H
490 loaded is in the I (invalid) state, i.e, a cache miss.
492 does not issue a RFO prefetch.
493 This is a demand RFO request
495 .Pq Event 27H , Umask 02H
498 The L1D prefetcher does not issue a RFO prefetch.
499 This is a demand RFO request.
501 .Pq Event 27H , Umask 08H
504 The L1D prefetcher does not issue a RFO prefetch.
505 This is a demand RFO request.
507 .Pq Event 27H , Umask 0EH
510 The L1D prefetcher does not issue a RFO
512 This is a demand RFO request
514 .Pq Event 27H , Umask 0FH
515 Counts all L2 store RFO requests.The L1D prefetcher does not issue a RFO
517 This is a demand RFO request.
519 .Pq Event 27H , Umask 10H
521 loaded is in the I (invalid) state, i.e. a cache miss.
523 .Pq Event 27H , Umask 20H
527 .Pq Event 27H , Umask 40H
531 .Pq Event 27H , Umask 80H
535 .Pq Event 27H , Umask E0H
539 .Pq Event 27H , Umask F0H
542 .Pq Event 28H , Umask 01H
544 is in the I (invalid) state, i.e. a cache miss.
546 .Pq Event 28H , Umask 02H
550 .Pq Event 28H , Umask 04H
554 .Pq Event 28H , Umask 08H
558 .Pq Event 28H , Umask 0FH
561 .Pq Event 2EH , Umask 02H
564 sizes and other implementation-specific characteristics; value comparison to
566 See Table A-1.
568 .Pq Event 2EH , Umask 01H
571 and other implementation-specific characteristics; value comparison to
573 See Table A-1.
575 .Pq Event 3CH , Umask 00H
576 Counts the number of thread cycles while the thread is not in a halt state.
580 see Table A-1
582 .Pq Event 3CH , Umask 01H
584 see Table A-1
586 .Pq Event 49H , Umask 01H
587 Counts the number of misses in the STLB which causes a page walk.
589 .Pq Event 49H , Umask 02H
590 Counts number of misses in the STLB which resulted in a completed page walk.
592 .Pq Event 49H , Umask 04H
595 .Pq Event 49H , Umask 10H
600 .Pq Event 49H , Umask 80H
603 .Pq Event 4CH , Umask 01H
604 Counts load operations sent to the L1 data cache while a previous SSE
608 .Pq Event 4EH , Umask 01H
612 .Pq Event 4EH , Umask 02H
616 A streamer, which predicts lines sequentially after
622 .Pq Event 4EH , Umask 04H
630 .Pq Event 4FH , Umask 10H
633 .Pq Event 51H , Umask 01H
637 .Pq Event 51H , Umask 02H
641 .Pq Event 51H , Umask 04H
646 .Pq Event 51H , Umask 08H
651 .Pq Event 52H , Umask 01H
655 .Pq Event 53H , Umask 01H
659 .Pq Event 60H , Umask 01H
664 .Pq Event 60H , Umask 02H
669 .Pq Event 60H , Umask 04H
674 .Pq Event 60H , Umask 08H
679 .Pq Event 63H , Umask 01H
681 A lock is asserted when
682 there is a locked memory access, due to uncacheable memory, a locked
683 operation that spans two cache lines, or a page walk from an uncacheable
686 L1D and L2 locks have a very high performance penalty and
689 .Pq Event 63H , Umask 02H
694 .Pq Event 6CH , Umask 01H
697 .Pq Event 80H , Umask 01H
700 .Pq Event 80H , Umask 02H
708 .Pq Event 80H , Umask 03H
712 .Pq Event 80H , Umask 04H
713 Cycle counts for which an instruction fetch stalls due to a L1I cache miss,
716 .Pq Event 82H , Umask 01H
719 .Pq Event 85H , Umask 01H
720 Counts the number of misses in all levels of the ITLB which causes a page
723 .Pq Event 85H , Umask 02H
724 Counts number of misses in all levels of the ITLB which resulted in a
727 .Pq Event 85H , Umask 04H
730 .Pq Event 85H , Umask 80H
733 .Pq Event 87H , Umask 01H
738 .Pq Event 87H , Umask 02H
742 .Pq Event 87H , Umask 04H
743 Stall cycles due to a full instruction queue.
745 .Pq Event 87H , Umask 08H
748 .Pq Event 87H , Umask 0FH
751 .Pq Event 88H , Umask 01H
755 .Pq Event 88H , Umask 02H
759 .Pq Event 88H , Umask 04H
763 .Pq Event 88H , Umask 07H
767 .Pq Event 88H , Umask 08H
768 Counts indirect near branches that have a return mnemonic.
770 .Pq Event 88H , Umask 10H
774 .Pq Event 88H , Umask 20H
778 .Pq Event 88H , Umask 30H
781 .Pq Event 88H , Umask 40H
784 .Pq Event 88H , Umask 7FH
786 This includes only instructions and not micro-op branches.
787 Frequent branching is not necessarily a major performance issue.
788 However frequent branch mispredictions may be a problem.
790 .Pq Event 89H , Umask 01H
794 .Pq Event 89H , Umask 02H
798 .Pq Event 89H , Umask 04H
802 .Pq Event 89H , Umask 07H
806 .Pq Event 89H , Umask 08H
807 Counts mispredicted indirect branches that have a rear return mnemonic.
809 .Pq Event 89H , Umask 10H
810 Counts mispredicted non-indirect near calls executed, (should always be 0).
812 .Pq Event 89H , Umask 20H
816 .Pq Event 89H , Umask 30H
820 .Pq Event 89H , Umask 40H
824 .Pq Event 89H , Umask 7FH
828 .Pq Event A2H , Umask 01H
839 .Pq Event A2H , Umask 02H
842 .Pq Event A2H , Umask 04H
846 A high count of this event indicates that there are long latency
853 .Pq Event A2H , Umask 08H
854 This event counts the number of cycles that a resource related stall will
857 The stall ends when a store
860 .Pq Event A2H , Umask 10H
861 Counts the cycles of stall due to re- order buffer full.
863 .Pq Event A2H , Umask 20H
865 floating-point unit (FPU) control word.
867 .Pq Event A2H , Umask 40H
868 Stalls due to the MXCSR register rename occurring to close to a previous
872 .Pq Event A2H , Umask 80H
876 .Pq Event A6H , Umask 01H
877 Counts the number of instructions decoded that are macro-fused but not
880 .Pq Event A7H , Umask 01H
881 Counts number of times a BACLEAR was forced by the Instruction Queue.
883 direction based on a static scheme and dynamic data provided by the L2
887 the Branch Address Calculator to issue a BACLEAR.
892 .Pq Event A8H , Umask 01H
893 Counts the number of micro-ops delivered by loop stream detector
896 .Pq Event AEH , Umask 01H
899 .Pq Event B0H , Umask 01H
903 .Pq Event B0H , Umask 02H
907 .Pq Event B0H , Umask 04H
911 .Pq Event B0H , Umask 08H
915 .Pq Event 80H , Umask 10H
919 .Pq Event B0H , Umask 40H
922 .Pq Event B0H , Umask 80H
925 .Pq Event B1H , Umask 01H
929 .Pq Event B1H , Umask 02H
934 .Pq Event B1H , Umask 04H
937 This is a core count only and can not be collected per
940 .Pq Event B1H , Umask 08H
943 This is a core count only and can not be collected per thread.
945 .Pq Event B1H , Umask 10H
948 This is a core count only and can not be collected per thread.
952 issued on ports 0-4.
953 This is a core count only and can not be collected per thread.
955 .Pq Event B1H , Umask 20H
961 This is a core count only and can not be collected per thread.
963 .Pq Event B1H , Umask 40H
967 .Pq Event B1H , Umask 80H
970 .Pq Event B2H , Umask 01H
971 Counts number of cycles the SQ is full to handle off-core requests.
973 .Pq Event B3H , Umask 01H
978 .Pq Event B3H , Umask 02H
983 .Pq Event B3H , Umask 04H
988 .Pq Event B4H , Umask 01H
991 .Pq Event B4H , Umask 02H
994 .Pq Event B4H , Umask 04H
997 .Pq Event B7H , Umask 01H
998 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
1002 .Pq Event B8H , Umask 01H
1003 Counts HIT snoop response sent by this thread in response to a snoop
1006 .Pq Event B8H , Umask 02H
1007 Counts HIT E snoop response sent by this thread in response to a snoop
1010 .Pq Event B8H , Umask 04H
1011 Counts HIT M snoop response sent by this thread in response to a snoop
1014 .Pq Event BBH , Umask 01H
1015 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
1019 .Pq Event C0H , Umask 01H
1020 See Table A-1
1021 Notes: INST_RETIRED.ANY is counted by a designated fixed counter.
1022 INST_RETIRED.ANY_P is counted by a programmable counter and is an
1024 Event is supported if CPUID.A.EBX[1] = 0.
1028 .Pq Event C0H , Umask 02H
1031 sub-operations of complex floating point instructions like transcendental
1034 .Pq Event C0H , Umask 04H
1037 .Pq Event C2H , Umask 01H
1038 Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
1040 Most instructions are composed of one or two micro-ops.
1046 .Pq Event C2H , Umask 02H
1049 .Pq Event C2H , Umask 04H
1050 Counts number of macro-fused uops retired.
1052 .Pq Event C3H , Umask 01H
1055 .Pq Event C3H , Umask 02H
1058 .Pq Event C3H , Umask 04H
1059 Counts the number of times that a program writes to a code section.
1060 Self-modifying code causes a sever penalty in all Intel 64 and IA-32
1064 .Pq Event C4H , Umask 00H
1065 See Table A-1.
1067 .Pq Event C4H , Umask 01H
1070 .Pq Event C4H , Umask 02H
1073 .Pq Event C4H , Umask 04H
1076 .Pq Event C5H , Umask 00H
1077 See Table A-1.
1079 .Pq Event C5H , Umask 01H
1082 .Pq Event C5H , Umask 02H
1085 .Pq Event C5H , Umask 04H
1088 .Pq Event C7H , Umask 01H
1089 Counts SIMD packed single-precision floating point Uops retired.
1091 .Pq Event C7H , Umask 02H
1092 Counts SIMD calar single-precision floating point Uops retired.
1094 .Pq Event C7H , Umask 04H
1095 Counts SIMD packed double- precision floating point Uops retired.
1097 .Pq Event C7H , Umask 08H
1098 Counts SIMD scalar double-precision floating point Uops retired.
1100 .Pq Event C7H , Umask 10H
1101 Counts 128-bit SIMD vector integer Uops retired.
1103 .Pq Event C8H , Umask 20H
1107 .Pq Event CBH , Umask 01H
1110 .Pq Event CBH , Umask 02H
1113 .Pq Event CBH , Umask 04H
1117 .Pq Event CBH , Umask 08H
1118 Counts number of retired loads that hit in a sibling core's L2 (on die
1123 .Pq Event CBH , Umask 10H
1125 The load was satisfied by a remote socket, local memory or an IOH.
1127 .Pq Event CBH , Umask 40H
1132 .Pq Event CBH , Umask 80H
1134 The DTLB miss is not counted if the load operation causes a fault.
1139 .Pq Event CCH , Umask 01H
1140 Counts the first floating-point instruction following any MMX instruction.
1142 floating-point and MMX technology states.
1144 .Pq Event CCH , Umask 02H
1145 Counts the first MMX instruction following a floating-point instruction.
1147 floating-point and MMX technology states.
1149 .Pq Event CCH , Umask 03H
1153 floating-point and MMX technology states.
1155 .Pq Event D0H , Umask 01H
1159 .Pq Event D1H , Umask 01H
1162 .Pq Event D1H , Umask 02H
1164 The MS delivers uops when the instruction is more than 4 uops long or a
1167 .Pq Event D1H , Umask 04H
1170 ESP instructions do not generate a Uop to increment or decrement ESP.
1174 .Pq Event D1H , Umask 08H
1179 .Pq Event D2H , Umask 01H
1181 reasons, one of which is a partial flag register stall.
1182 A partial register
1188 .Pq Event D2H , Umask 02H
1190 longer than the defined latency because the instruction used a register that
1193 .Pq Event D2H , Umask 04H
1195 not allow new micro-ops to enter the out-of-order pipeline.
1198 and prevent the stalled micro-ops from entering the pipe.
1199 In such a case,
1200 micro-ops retry entering the execution pipe in the next cycle and the
1201 ROB-read port stall is counted again.
1203 .Pq Event D2H , Umask 08H
1210 read port stalls occurred, which did not allow new micro-ops to enter the
1213 flag stalls occurred Cycles floating-point unit (FPU) status word stalls
1219 .Pq Event D4H , Umask 01H
1222 If a segment is renamed but not
1223 retired and a second update to the same segment occurs, a stall occurs in
1224 the front- end of the pipeline until the renamed segment retires.
1226 .Pq Event D5H , Umask 01H
1229 .Pq Event DBH , Umask 01H
1230 Counts unfusion events due to floating point exception to a fused uop.
1232 .Pq Event E0H , Umask 01H
1235 .Pq Event E5H , Umask 01H
1236 Counts number of times the Branch Prediction Unit missed predicting a call
1239 .Pq Event E6H , Umask 01H
1241 Branch Prediction Unit cannot provide a correct prediction and this is
1249 .Pq Event E6H , Umask 02H
1251 conditional branch instructions in which there was a target hit but the
1256 .Pq Event E8H , Umask 01H
1257 Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken
1261 .Pq Event E8H , Umask 02H
1264 The PBU clear leads to a 3 cycle bubble in the Front End.
1266 .Pq Event ECH , Umask 01H
1269 .Pq Event F0H , Umask 01H
1272 .Pq Event F0H , Umask 02H
1275 .Pq Event F0H , Umask 04H
1278 .Pq Event F0H , Umask 08H
1281 .Pq Event F0H , Umask 10H
1284 .Pq Event F0H , Umask 20H
1288 .Pq Event F0H , Umask 40H
1291 .Pq Event F0H , Umask 80H
1294 .Pq Event F1H , Umask 02H
1298 .Pq Event F1H , Umask 04H
1302 .Pq Event F1H , Umask 07H
1305 .Pq Event F2H , Umask 01H
1306 Counts L2 clean cache lines evicted by a demand request.
1308 .Pq Event F2H , Umask 02H
1309 Counts L2 dirty (modified) cache lines evicted by a demand request.
1311 .Pq Event F2H , Umask 04H
1312 Counts L2 clean cache line evicted by a prefetch request.
1314 .Pq Event F2H , Umask 08H
1315 Counts L2 modified cache line evicted by a prefetch request.
1320 .Pq Event F4H , Umask 04H
1323 .Pq Event F4H , Umask 10H
1324 Counts the number of SQ lock splits across a cache line.
1326 .Pq Event F6H , Umask 01H
1330 .Pq Event F7H , Umask 01H
1332 micro-code assist intervention.
1336 loaded to a register or used as input from memory, Division by 0 or
1339 .Pq Event F7H , Umask 02H
1340 Counts number of floating point micro-code assist when the output value
1343 .Pq Event F7H , Umask 04H
1344 Counts number of floating point micro-code assist when the input value (one
1347 .Pq Event FDH , Umask 01H
1350 .Pq Event FDH , Umask 02H
1353 .Pq Event FDH , Umask 04H
1356 .Pq Event FDH , Umask 08H
1359 .Pq Event FDH , Umask 10H
1362 .Pq Event FDH , Umask 20H
1365 .Pq Event FDH , Umask 40H