Lines Matching +full:a +full:- +full:h

14 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
98 (RFO) requests generated by a write to data cacheline.
113 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
120 and was serviced by another core with a cross core snoop where no modified
124 and was serviced by another core with a cross core snoop where modified
128 by forwarded data following a cross package snoop where no modified
137 Non-DRAM requests that were serviced by IOH.
141 events measured in a cycle is greater than or equal to
144 Configure the PMC to count the number of de-asserted to asserted
146 If specified, the counter will increment only once whenever a
171 .Bl -tag -width indent
173 .Pq Event 04H , Umask 07H
176 .Pq Event 06H , Umask 04H
177 Counts number of loads delayed with at-Retirement block code.
183 .Pq Event 06H , Umask 08H
186 .Pq Event 07H , Umask 01H
189 .Pq Event 08H , Umask 01H
190 Counts all load misses that cause a page walk
192 .Pq Event 08H , Umask 02H
195 .Pq Event 08H , Umask 10H
198 .Pq Event 08H , Umask 20H
202 .Pq Event 08H , Umask 80H
205 .Pq Event 0BH , Umask 01H
206 Counts the number of instructions with an architecturally-visible store
210 .Pq Event 0BH , Umask 02H
211 Counts the number of instructions with an architecturally-visible store
215 .Pq Event 0BH , Umask 10H
220 .Pq Event 0CH , Umask 01H
222 The DTLB miss is not counted if the store operation causes a fault.
226 .Pq Event 0EH , Umask 01H
231 .Pq Event 0EH , Umask 01H
237 .Pq Event 0EH , Umask 02H
241 .Pq Event 0FH , Umask 01H
246 .Pq Event 0FH , Umask 02H
248 hit modified data in a sibling core residing on the same socket.
250 .Pq Event 0FH , Umask 08H
252 missed the L1, L2 and L3 caches and HIT in a remote socket's cache.
255 .Pq Event 0FH , Umask 10H
258 This includes both DRAM access and HITM in a remote socket's cache
261 .Pq Event 0FH , Umask 20H
263 missed the L1, L2 and L3 caches and required a local socket memory
265 This includes locally homed cachelines that were in a modified
268 .Pq Event 0FH , Umask 80H
273 .Pq Event 10H , Umask 01H
277 This event does not distinguish an FADD used in the middle of a transcendental flow from a separate…
279 .Pq Event 10H , Umask 02H
282 .Pq Event 10H , Umask 04H
285 .Pq Event 10H , Umask 08H
288 .Pq Event 10H , Umask 10H
291 .Pq Event 10H , Umask 20H
294 .Pq Event 10H , Umask 40H
297 .Pq Event 10H , Umask 80H
300 .Pq Event 12H , Umask 01H
303 .Pq Event 12H , Umask 02H
306 .Pq Event 12H , Umask 04H
309 .Pq Event 12H , Umask 08H
312 .Pq Event 12H , Umask 10H
315 .Pq Event 12H , Umask 20H
318 .Pq Event 12H , Umask 40H
321 .Pq Event 13H , Umask 01H
325 .Pq Event 13H , Umask 02H
328 one-cycle delayed staging latch before it is written into the LB.
330 .Pq Event 13H , Umask 04H
334 .Pq Event 13H , Umask 07H
337 .Pq Event 14H , Umask 01H
345 .Pq Event 14H , Umask 02H
350 .Pq Event 17H , Umask 01H
354 .Pq Event 18H , Umask 01H
358 .Pq Event 19H , Umask 01H
361 .Pq Event 1EH , Umask 01H
368 decode enough instructions per cycle to sustain the 4-wide pipeline.
373 .Pq Event 20H , Umask 01H
376 .Pq Event 24H , Umask 01H
382 .Pq Event 24H , Umask 02H
386 .Pq Event 24H , Umask 03H
390 .Pq Event 24H , Umask 04H
396 .Pq Event 24H , Umask 08H
400 .Pq Event 24H , Umask 0CH
404 .Pq Event 24H , Umask 10H
409 .Pq Event 24H , Umask 20H
414 .Pq Event 24H , Umask 30H
418 .Pq Event 24H , Umask 40H
421 .Pq Event 24H , Umask 80H
424 .Pq Event 24H , Umask C0H
427 .Pq Event 24H , Umask AAH
430 .Pq Event 24H , Umask FFH
433 .Pq Event 26H , Umask 01H
435 in the I (invalid) state, i.e. a cache miss.
438 .Pq Event 26H , Umask 02H
443 .Pq Event 26H , Umask 04H
448 .Pq Event 26H , Umask 08H
453 .Pq Event 26H , Umask 0FH
457 .Pq Event 26H , Umask 10H
459 in the I (invalid) state, i.e. a cache miss.
461 .Pq Event 26H , Umask 20H
464 A prefetch RFO will miss on an S state line, while a prefetch read will
467 .Pq Event 26H , Umask 40H
471 .Pq Event 26H , Umask 80H
475 .Pq Event 26H , Umask F0H
478 .Pq Event 26H , Umask FFH
481 .Pq Event 27H , Umask 01H
483 loaded is in the I (invalid) state, i.e, a cache miss.
484 The L1D prefetcher does not issue a RFO prefetch.
485 This is a demand RFO request
487 .Pq Event 27H , Umask 02H
490 The L1D prefetcher does not issue a RFO prefetch.
491 This is a demand RFO request
493 .Pq Event 27H , Umask 08H
496 The L1D prefetcher does not issue a RFO prefetch.
497 This is a demand RFO request
499 .Pq Event 27H , Umask 0EH
502 The L1D prefetcher does not issue a RFO prefetch.
503 This is a demand RFO request
505 .Pq Event 27H , Umask 0FH
507 The L1D prefetcher does not issue a RFO prefetch.
508 This is a demand RFO request
510 .Pq Event 27H , Umask 10H
512 loaded is in the I (invalid) state, i.e. a cache miss.
514 .Pq Event 27H , Umask 20H
518 .Pq Event 27H , Umask 40H
522 .Pq Event 27H , Umask 80H
526 .Pq Event 27H , Umask E0H
530 .Pq Event 27H , Umask F0H
533 .Pq Event 28H , Umask 01H
535 is in the I (invalid) state, i.e. a cache miss.
537 .Pq Event 28H , Umask 02H
541 .Pq Event 28H , Umask 04H
545 .Pq Event 28H , Umask 08H
549 .Pq Event 28H , Umask 0FH
553 This event counts requests originating from the core that reference a cache
556 due to a L2 hardware-prefetch.
557 Because cache hierarchy, cache sizes and other implementation-specific
559 see Table A-1
561 .Pq Event 2EH , Umask 41H
565 line fills due to L2 hardware-prefetches.
566 Because cache hierarchy, cache sizes and other implementation-specific
568 see Table A-1
570 .Pq Event 3CH , Umask 00H
571 Counts the number of thread cycles while the thread is not in a halt state.
574 see Table A-1
576 .Pq Event 3CH , Umask 01H
578 see Table A-1
580 .Pq Event 40H , Umask 01H
585 .Pq Event 40H , Umask 02H
590 .Pq Event 40H , Umask 04H
595 .Pq Event 40H , Umask 08H
600 .Pq Event 40H , Umask 0FH
604 .Pq Event 41H , Umask 02H
609 .Pq Event 41H , Umask 04H
614 .Pq Event 41H , Umask 08H
619 .Pq Event 42H , Umask 01H
626 .Pq Event 42H , Umask 02H
631 .Pq Event 42H , Umask 04H
636 .Pq Event 42H , Umask 08H
641 .Pq Event 43H , Umask 01H
645 For example, a load blocked by unknown store address and later performed
647 The event does not include non- memory accesses, such as I/O accesses.
650 .Pq Event 43H , Umask 02H
655 .Pq Event 49H , Umask 01H
656 Counts the number of misses in the STLB which causes a page walk.
658 .Pq Event 49H , Umask 02H
659 Counts number of misses in the STLB which resulted in a completed page walk.
661 .Pq Event 49H , Umask 10H
665 .Pq Event 49H , Umask 20H
668 .Pq Event 49H , Umask 80H
669 Counts number of misses in the STLB which resulted in a completed page walk for large pages.
671 .Pq Event 4CH , Umask 01H
672 Counts load operations sent to the L1 data cache while a previous SSE
676 .Pq Event 4EH , Umask 01H
680 .Pq Event 4EH , Umask 02H
683 A streamer, which predicts lines sequentially after this one should be fetched,
687 .Pq Event 4EH , Umask 04H
694 .Pq Event 51H , Umask 01H
698 .Pq Event 51H , Umask 02H
702 .Pq Event 51H , Umask 04H
707 .Pq Event 51H , Umask 08H
712 .Pq Event 52H , Umask 01H
716 .Pq Event 53H , Umask 01H
720 .Pq Event 63H , Umask 01H
722 A lock is asserted when there is a locked memory access, due to uncacheable memory, a locked
723 operation that spans two cache lines, or a page walk from an uncacheable
726 L1D and L2 locks have a very high performance penalty and it is highly recommended to
729 .Pq Event 63H , Umask 02H
734 .Pq Event 6CH , Umask 01H
737 .Pq Event 80H , Umask 01H
740 .Pq Event 80H , Umask 02H
747 .Pq Event 80H , Umask 03H
751 .Pq Event 80H , Umask 04H
752 Cycle counts for which an instruction fetch stalls due to a L1I cache miss,
755 .Pq Event 82H , Umask 01H
758 .Pq Event 85H , Umask 01H
759 Counts the number of misses in all levels of the ITLB which causes a page
762 .Pq Event 85H , Umask 02H
763 Counts number of misses in all levels of the ITLB which resulted in a
766 .Pq Event 87H , Umask 01H
771 .Pq Event 87H , Umask 02H
775 .Pq Event 87H , Umask 04H
776 Stall cycles due to a full instruction queue.
778 .Pq Event 87H , Umask 08H
781 .Pq Event 87H , Umask 0FH
784 .Pq Event 88H , Umask 01H
788 .Pq Event 88H , Umask 02H
792 .Pq Event 88H , Umask 04H
796 .Pq Event 88H , Umask 07H
800 .Pq Event 88H , Umask 08H
801 Counts indirect near branches that have a return mnemonic.
803 .Pq Event 88H , Umask 10H
807 .Pq Event 88H , Umask 20H
811 .Pq Event 88H , Umask 30H
814 .Pq Event 88H , Umask 40H
817 .Pq Event 88H , Umask 7FH
819 This includes only instructions and not micro-op branches.
820 Frequent branching is not necessarily a major performance issue.
821 However frequent branch mispredictions may be a problem.
823 .Pq Event 89H , Umask 01H
827 .Pq Event 89H , Umask 02H
831 .Pq Event 89H , Umask 04H
835 .Pq Event 89H , Umask 07H
839 .Pq Event 89H , Umask 08H
840 Counts mispredicted indirect branches that have a rear return mnemonic.
842 .Pq Event 89H , Umask 10H
843 Counts mispredicted non-indirect near calls executed, (should always be 0).
845 .Pq Event 89H , Umask 20H
849 .Pq Event 89H , Umask 30H
853 .Pq Event 89H , Umask 40H
857 .Pq Event 89H , Umask 7FH
861 .Pq Event A2H , Umask 01H
871 .Pq Event A2H , Umask 02H
874 .Pq Event A2H , Umask 04H
877 A high count of this event indicates that there are long latency
884 .Pq Event A2H , Umask 08H
885 This event counts the number of cycles that a resource related stall will
888 The stall ends when a store instruction commits its data to the cache or memory.
890 .Pq Event A2H , Umask 10H
891 Counts the cycles of stall due to re- order buffer full.
893 .Pq Event A2H , Umask 20H
895 floating-point unit (FPU) control word.
897 .Pq Event A2H , Umask 40H
898 Stalls due to the MXCSR register rename occurring to close to a previous
902 .Pq Event A2H , Umask 80H
906 .Pq Event A6H , Umask 01H
907 Counts the number of instructions decoded that are macro-fused but not
910 .Pq Event A7H , Umask 01H
911 Counts number of times a BACLEAR was forced by the Instruction Queue.
913 based on a static scheme and dynamic data provided by the L2 Branch
917 the Branch Address Calculator to issue a BACLEAR.
921 .Pq Event A8H , Umask 01H
922 Counts the number of micro-ops delivered by loop stream detector
925 .Pq Event AEH , Umask 01H
928 .Pq Event B0H , Umask 40H
931 .Pq Event B1H , Umask 01H
935 .Pq Event B1H , Umask 02H
939 .Pq Event B1H , Umask 04H
942 This is a core count only and can not be collected per thread.
944 .Pq Event B1H , Umask 08H
947 This is a core count only and can not be collected per thread.
949 .Pq Event B1H , Umask 10H
952 This is a core count only and can not be collected per thread.
958 Invert=1 to count P0-4 stalled cycles Use Cmask=1, Edge=1, Invert=1 to count
959 P0-4 stalls.
961 .Pq Event B1H , Umask 20H
966 Use Cmask=1 for active cycles; Cmask=0 for weighted cycles; Use CMask=1, Invert=1 to count P0-4 sta…
967 cycles Use Cmask=1, Edge=1, Invert=1 to count P0-4 stalls.
969 .Pq Event B1H , Umask 40H
973 .Pq Event B1H , Umask 80H
976 .Pq Event B2H , Umask 01H
977 Counts number of cycles the SQ is full to handle off-core requests.
979 .Pq Event B7H , Umask 01H
980 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
984 .Pq Event B8H , Umask 01H
985 Counts HIT snoop response sent by this thread in response to a snoop
988 .Pq Event B8H , Umask 02H
989 Counts HIT E snoop response sent by this thread in response to a snoop
992 .Pq Event B8H , Umask 04H
993 Counts HIT M snoop response sent by this thread in response to a snoop
996 .Pq Event BBH , Umask 01H
997 see Section 30.6.1.3, Off-core Response Performance Monitoring in the
1001 .Pq Event C0H , Umask 01H
1002 See Table A-1
1003 Notes: INST_RETIRED.ANY is counted by a designated fixed counter.
1004 INST_RETIRED.ANY_P is counted by a programmable counter and is an
1006 Event is supported if CPUID.A.EBX[1] = 0.
1010 .Pq Event C0H , Umask 02H
1013 .Pq Event C0H , Umask 04H
1016 sub-operations of complex floating point instructions like transcendental
1019 .Pq Event C2H , Umask 01H
1020 Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2,
1022 Most instructions are composed of one or two micro-ops.
1027 .Pq Event C2H , Umask 02H
1030 .Pq Event C2H , Umask 04H
1031 Counts number of macro-fused uops retired.
1033 .Pq Event C3H , Umask 01H
1036 .Pq Event C3H , Umask 02H
1039 .Pq Event C3H , Umask 04H
1040 Counts the number of times that a program writes to a code section.
1041 Self-modifying code causes a sever penalty in all Intel 64 and IA-32
1045 .Pq Event C4H , Umask 00H
1046 See Table A-1
1048 .Pq Event C4H , Umask 01H
1051 .Pq Event C4H , Umask 02H
1054 .Pq Event C4H , Umask 04H
1057 .Pq Event C5H , Umask 00H
1058 See Table A-1
1060 .Pq Event C5H , Umask 02H
1063 .Pq Event C7H , Umask 01H
1064 Counts SIMD packed single-precision floating point Uops retired.
1066 .Pq Event C7H , Umask 02H
1067 Counts SIMD calar single-precision floating point Uops retired.
1069 .Pq Event C7H , Umask 04H
1070 Counts SIMD packed double- precision floating point Uops retired.
1072 .Pq Event C7H , Umask 08H
1073 Counts SIMD scalar double-precision floating point Uops retired.
1075 .Pq Event C7H , Umask 10H
1076 Counts 128-bit SIMD vector integer Uops retired.
1078 .Pq Event C8H , Umask 20H
1082 .Pq Event CBH , Umask 01H
1085 .Pq Event CBH , Umask 02H
1088 .Pq Event CBH , Umask 04H
1092 .Pq Event CBH , Umask 08H
1093 Counts number of retired loads that hit in a sibling core's L2 (on die core).
1097 .Pq Event CBH , Umask 10H
1099 The load was satisfied by a remote socket, local memory or an IOH.
1101 .Pq Event CBH , Umask 40H
1106 .Pq Event CBH , Umask 80H
1108 The DTLB miss is not counted if the load operation causes a fault.
1113 .Pq Event CCH , Umask 01H
1114 Counts the first floating-point instruction following any MMX instruction.
1116 floating-point and MMX technology states.
1118 .Pq Event CCH , Umask 02H
1119 Counts the first MMX instruction following a floating-point instruction.
1121 floating-point and MMX technology states.
1123 .Pq Event CCH , Umask 03H
1127 floating-point and MMX technology states.
1129 .Pq Event D0H , Umask 01H
1133 .Pq Event D1H , Umask 02H
1135 The MS delivers uops when the instruction is more than 4 uops long or a microcode
1138 .Pq Event D1H , Umask 04H
1141 ESP instructions do not generate a Uop to increment or decrement ESP.
1145 .Pq Event D1H , Umask 08H
1150 .Pq Event D2H , Umask 01H
1152 reasons, one of which is a partial flag register stall.
1153 A partial register stall may occur when two conditions are met: 1) an instruction modifies
1158 .Pq Event D2H , Umask 02H
1160 longer than the defined latency because the instruction used a register that
1163 .Pq Event D2H , Umask 04H
1165 not allow new micro-ops to enter the out-of-order pipeline.
1167 the same cycle and prevent the stalled micro-ops from entering the pipe.
1168 In such a case, micro-ops retry entering the execution pipe in the next
1169 cycle and the ROB-read port stall is counted again.
1171 .Pq Event D2H , Umask 08H
1178 read port stalls occurred, which did not allow new micro-ops to enter the
1181 Cycles floating-point unit (FPU) status word stalls occurred.
1186 .Pq Event D4H , Umask 01H
1189 If a segment is renamed but not retired and a second update to the same
1190 segment occurs, a stall occurs in the front-end of the pipeline until the
1193 .Pq Event D5H , Umask 01H
1196 .Pq Event DBH , Umask 01H
1197 Counts unfusion events due to floating point exception to a fused uop.
1199 .Pq Event E0H , Umask 01H
1202 .Pq Event E5H , Umask 01H
1203 Counts number of times the Branch Prediction Unit missed predicting a call
1206 .Pq Event E6H , Umask 01H
1208 Branch Prediction Unit cannot provide a correct prediction and this is
1216 .Pq Event E6H , Umask 02H
1218 conditional branch instructions in which there was a target hit but the
1223 .Pq Event E8H , Umask 01H
1224 Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken
1228 .Pq Event E8H , Umask 02H
1230 The PBU clear leads to a 3 cycle bubble in the Front End.
1232 .Pq Event F0H , Umask 01H
1235 .Pq Event F0H , Umask 02H
1238 .Pq Event F0H , Umask 04H
1241 .Pq Event F0H , Umask 08H
1244 .Pq Event F0H , Umask 10H
1247 .Pq Event F0H , Umask 20H
1251 .Pq Event F0H , Umask 40H
1254 .Pq Event F0H , Umask 80H
1257 .Pq Event F1H , Umask 02H
1261 .Pq Event F1H , Umask 04H
1265 .Pq Event F1H , Umask 07H
1268 .Pq Event F2H , Umask 01H
1269 Counts L2 clean cache lines evicted by a demand request.
1271 .Pq Event F2H , Umask 02H
1272 Counts L2 dirty (modified) cache lines evicted by a demand request.
1274 .Pq Event F2H , Umask 04H
1275 Counts L2 clean cache line evicted by a prefetch request.
1277 .Pq Event F2H , Umask 08H
1278 Counts L2 modified cache line evicted by a prefetch request.
1283 .Pq Event F4H , Umask 10H
1284 Counts the number of SQ lock splits across a cache line.
1286 .Pq Event F6H , Umask 01H
1290 .Pq Event F7H , Umask 01H
1292 micro-code assist intervention.
1296 loaded to a register or used as input from memory, Division by 0 or
1299 .Pq Event F7H , Umask 02H
1300 Counts number of floating point micro-code assist when the output value
1303 .Pq Event F7H , Umask 04H
1304 Counts number of floating point micro-code assist when the input value (one
1307 .Pq Event FDH , Umask 01H
1310 .Pq Event FDH , Umask 02H
1313 .Pq Event FDH , Umask 04H
1316 .Pq Event FDH , Umask 08H
1319 .Pq Event FDH , Umask 10H
1322 .Pq Event FDH , Umask 20H
1325 .Pq Event FDH , Umask 40H
1331 .Bl -tag -width indent
1333 .Pq Event 02H , Umask 01H
1336 .Pq Event 03H , Umask 01H
1337 Counts the number of loads blocked by a preceding store with unknown data.
1339 .Pq Event 03H , Umask 04H
1340 Counts the number of loads blocked by a preceding store address.
1342 .Pq Event 01H , Umask 04H
1345 .Pq Event 05H , Umask 01H
1348 .Pq Event 05H , Umask 02H
1351 .Pq Event 05H , Umask 03H
1354 .Pq Event 06H , Umask 01H
1359 .Pq Event 06H , Umask 02H
1363 .Pq Event 06H , Umask 0FH
1366 .Pq Event 09H , Umask 01H
1369 .Pq Event 09H , Umask 02H
1372 .Pq Event 09H , Umask 04H
1375 .Pq Event 09H , Umask 08H
1379 .Pq Event 1DH , Umask 01H
1382 .Pq Event 1DH , Umask 02H
1385 .Pq Event 1DH , Umask 04H
1388 .Pq Event 04H , Umask 04H
1391 The L1D prefetcher does not issue a RFO prefetch.
1392 This is a demand RFO request
1394 .Pq Event 27H , Umask 04H
1397 .Pq Event 3DH , Umask 01H
1398 Counts micro-ops decoded by decoder 0.
1400 .Pq Event 01H , Umask 01H
1405 .Pq Event 41H , Umask 41H
1410 .Pq Event 49H , Umask 20H
1414 .Pq Event 49H , Umask 40H
1418 .Pq Event 49H , Umask 80H
1421 .Pq Event 4BH , Umask 01H
1422 Counts number of SSE NTA prefetch/weakly-ordered instructions which missed
1425 .Pq Event 4BH , Umask 08H
1428 .Pq Event 4DH , Umask 01H
1431 .Pq Event 4FH , Umask 02H
1436 .Pq Event 4FH , Umask 04H
1439 .Pq Event 4FH , Umask 08H
1442 .Pq Event 60H , Umask 01H
1447 .Pq Event 60H , Umask 02H
1452 .Pq Event 60H , Umask 04H
1457 .Pq Event 60H , Umask 08H
1462 .Pq Event 81H , Umask 01H
1465 .Pq Event 81H , Umask 02H
1468 .Pq Event 83H , Umask 01H
1471 .Pq Event 85H , Umask 04H
1474 .Pq Event 85H , Umask 04H
1477 .Pq Event 85H , Umask 10H
1480 .Pq Event 85H , Umask 20H
1484 .Pq Event 85H , Umask 40H
1488 .Pq Event 85H , Umask 80H
1491 .Pq Event 01H , Umask 80H
1495 .Pq Event B0H , Umask 02H
1499 .Pq Event B0H , Umask 04H
1503 .Pq Event B0H , Umask 08H
1507 .Pq Event B0H , Umask 10H
1511 .Pq Event B0H , Umask 20H
1514 .Pq Event B0H , Umask 80H
1517 .Pq Event B3H , Umask 01H
1521 .Pq Event B3H , Umask 02H
1525 .Pq Event B3H , Umask 04H
1529 .Pq Event BAH , Umask 04H
1532 .Pq Event BAH , Umask 02H
1533 Counts number of TPR writes one or two micro-ops.
1536 .Pq Event C3H , Umask 10H
1537 Counts the number of macro-fusion assists
1538 Counts SIMD packed single- precision floating point Uops retired.
1540 .Pq Event E4H , Umask 01H
1543 .Pq Event F3H , Umask 01H
1546 .Pq Event F3H , Umask 02H
1549 .Pq Event F3H , Umask 04H
1552 .Pq Event F3H , Umask 08H
1555 .Pq Event F3H , Umask 10H
1558 .Pq Event F3H , Umask 20H
1561 .Pq Event F4H , Umask 01H
1564 .Pq Event F4H , Umask 02H
1567 .Pq Event F4H , Umask 04H
1570 .Pq Event F4H , Umask 08H
1573 .Pq Event F8H , Umask 01H