Lines Matching +full:a +full:- +full:h

15 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual"
61 .%N "Order Number 325462-050US"
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Count matching events seen on any logical processor in a package.
92 events measured in a cycle is greater than or equal to
95 Configure the PMC to count the number of de-asserted to asserted
97 If specified, the counter will increment only once whenever a
121 Events that require core-specificity to be specified use a
127 .Bl -tag -width indent
143 .Bl -tag -width indent
153 Events that require a hardware prefetch qualifier to be specified use an
159 .Bl -tag -width "exclude"
171 Events that require a cache coherence qualifier to be specified use an
177 .Bl -tag -width indent
191 Events that require a snoop response qualifier to be specified use an
199 .Bl -tag -width indent
210 Events that require a snoop type qualifier use an additional qualifier
215 .Bl -tag -width indent
225 .Bl -tag -width indent
227 .Pq Event 03H , Umask 01H
232 .Pq Event 03H , Umask 02H
233 The cases where a forward was technically possible,
237 .Pq Event 03H , Umask 04H
241 .Pq Event 03H , Umask 08H
245 .Pq Event 03H , Umask 10H
251 .Pq Event 03H , Umask 20H
253 because there is not a store address buffer available.
255 .Pq Event 03H , Umask 40H
258 .Pq Event 03H , Umask 80H
261 .Pq Event 04H , Umask 01H
266 .Pq Event 04H , Umask 02H
267 The number of load micro-ops retired that hit L2.
269 .Pq Event 04H , Umask 04H
270 The number of load micro-ops retired that missed L2.
272 .Pq Event 04H , Umask 08H
275 .Pq Event 04H , Umask 10H
278 .Pq Event 04H , Umask 20H
282 .Pq Event 04H , Umask 40H
285 .Pq Event 04H , Umask 80H
288 .Pq Event 05H , Umask 01H
289 Every cycle when a D-side (walks due to a load) page walk is in progress.
291 page-walks.
295 .Pq Event 05H , Umask 02H
296 Every cycle when a I-side (walks due to an instruction fetch) page walk is in
299 page-walks.
301 .Pq Event 05H , Umask 03H
302 The number of times a data (D) page walk or an instruction (I) page walk is
304 Since a page walk implies a TLB miss, the number of TLB misses can be counted
307 .Pq Event 2EH , Umask 41H
314 references a cache line in the L2 cache.
317 .Pq Event 30H , Umask 00H
319 transactions that the L2 XQ rejects due to a full or near full
321 The XQ may reject transactions from the L2Q (non-cacheable
322 requests), BBS (L2 misses) and WOB (L2 write-back victims)
324 .Pq Event 31H , Umask 00H
326 requests rejected by the L2Q due to a full or nearly full condition which
329 rejected due to a full or nearly full condition, indicating back pressure from
331 The L2Q may also reject transactions from a core to insure fairness between
332 cores, or to delay a core's dirty eviction when the address conflicts incoming
337 .Pq Event 3CH , Umask 00H
338 The number of core cycles while the core is not in a halt state.
341 For this reason this event may have a changing ratio with regards to time.
343 .Pq Event 3CH , Umask 01H
344 The number of reference cycles that the core is not in a halt state.
350 .Pq Event 80H , Umask 01H
353 .Pq Event 80H , Umask 02H
360 .Pq Event 80H , Umask 03H
363 .Pq Event B6H , Umask 04H
365 This is a cumulative count of cycles the NIP stalled for all
368 .Pq Event B7H , Umask 01H
371 .Pq Event B7H , Umask 02H
374 .Pq Event C0H , Umask 00H
376 For instructions that consist of multiple micro-ops, this event counts the
377 retirement of the last micro-op of the instruction.
381 .Pq Event C2H , Umask 01H
382 The number of micro-ops retired that were supplied from MSROM.
384 .Pq Event C2H , Umask 10H
385 The number of micro-ops retired.
387 .Pq Event C3H , Umask 01H
388 The number of times that a program writes to a code section.
389 Self-modifying code causes a severe penalty in all Intel
392 .Pq Event C3H , Umask 02H
396 .Pq Event C3H , Umask 04H
400 .Pq Event C3H , Umask 08H
404 .Pq Event C4H , Umask 00H
434 .Pq Event C5H , Umask 00H
466 .Pq Event CAH , Umask 01H
470 .Pq Event CAH , Umask 20H
471 The number of cycles when no uops are allocated and a RATstall is
475 The number of cycles when the front-end does not provide any
478 .Pq Event CAH , Umask 50H
479 The number of cycles when the front-end does not provide any
482 .Pq Event CBH , Umask 01H
490 .Pq Event CDH , Umask 01H
493 .Pq Event E6H , Umask 01H
496 .Pq Event E6H , Umask 08H
499 .Pq Event E6H , Umask 10H
502 .Pq Event E7H , Umask 01H)
503 The number of times the MSROM starts a flow of UOPS.
523 .An -nosplit