Lines Matching +full:pll +full:- +full:mode
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18 <li class="inline"><a href="#pll">Phase-Lock Loop Operations</a></li>
24 …-lock feedback loop. It is an intricately crafted algorithm that automatically adapts for optimum…
28 <h4 id="pll">Clock Discipline Operations</h4>
29 …ed update <em>V<sub>s</sub></em>. The loop filter implements a type-2 proportional-integrator con…
30 …PLL mode the frequency predictor is an integral of the offset over past updates, while the phase p…
31 …PLL mode is determined by the <em>time constant</em>, which results in a "stiffness" dep…
33 … This would be described as oversampling by a factor of two. Finally, the PLL parameters have bee…
34 <p> It is important to understand how the dynamics of the PLL are affected by the time constant and…
36 …PLL is linear, the response with different offset step amplitudes and poll intervals has the same …
43 …reference implementation first measures the oscillator frequency over a five-min interval. This g…
44 … a frequency surge. This configuration is continued for an interval of five-min, after which the …
46 …ackup source, such as the local clock driver, ACTS modem driver or orphan mode is included in the …