Lines Matching refs:ins
12 class XtensaInst<int size, dag outs, dag ins, string asmstr, list<dag> pattern,
20 let InOperandList = ins;
29 class XtensaInst24<dag outs, dag ins, string asmstr, list<dag> pattern,
31 : XtensaInst<3, outs, ins, asmstr, pattern, itin> {
37 class XtensaInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
39 : XtensaInst<2, outs, ins, asmstr, pattern, itin> {
45 class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
47 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
60 class RRI4_Inst<bits<4> op0, bits<4> op1, dag outs, dag ins,
62 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
76 class RRI8_Inst<bits<4> op0, dag outs, dag ins,
78 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
91 class RI16_Inst<bits<4> op0, dag outs, dag ins,
93 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
102 class RSR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
104 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
115 class CALL_Inst<bits<4> op0, dag outs, dag ins,
117 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
126 class CALLX_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
128 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
143 class BRI8_Inst<bits<4> op0, dag outs, dag ins,
145 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
160 class BRI12_Inst<bits<4> op0, bits<2> n, bits<2> m, dag outs, dag ins,
162 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
173 class RRRN_Inst<bits<4> op0, dag outs, dag ins,
175 : XtensaInst16<outs, ins, asmstr, pattern, itin> {
186 class RI7_Inst<bits<4> op0, bits<1> i, dag outs, dag ins,
188 : XtensaInst16<outs, ins, asmstr, pattern, itin> {
199 class RI6_Inst<bits<4> op0, bits<1> i, bits<1> z, dag outs, dag ins,
201 : XtensaInst16<outs, ins, asmstr, pattern, itin> {
214 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
215 : XtensaInst<2, outs, ins, asmstr, pattern> {