Lines Matching +full:half +full:- +full:bit

1 //===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // InstrSchedModel annotations for out-of-order CPUs.
55 // Register-Memory operation.
57 // Register-Register operation.
131 def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
141 defm WriteIMul8 : X86SchedWritePair; // Integer 8-bit multiplication.
142 defm WriteIMul16 : X86SchedWritePair; // Integer 16-bit multiplication.
143 defm WriteIMul16Imm : X86SchedWritePair; // Integer 16-bit multiplication by immediate.
144 defm WriteIMul16Reg : X86SchedWritePair; // Integer 16-bit multiplication by register.
145 defm WriteIMul32 : X86SchedWritePair; // Integer 32-bit multiplication.
146 defm WriteIMul32Imm : X86SchedWritePair; // Integer 32-bit multiplication by immediate.
147 defm WriteIMul32Reg : X86SchedWritePair; // Integer 32-bit multiplication by register.
148 defm WriteIMul64 : X86SchedWritePair; // Integer 64-bit multiplication.
149 defm WriteIMul64Imm : X86SchedWritePair; // Integer 64-bit multiplication by immediate.
150 defm WriteIMul64Reg : X86SchedWritePair; // Integer 64-bit multiplication by register.
151 defm WriteMULX32 : X86SchedWritePair; // Integer 32-bit Multiplication without affecting flags.
152 defm WriteMULX64 : X86SchedWritePair; // Integer 64-bit Multiplication without affecting flags.
156 def WriteBSWAP32 : SchedWrite; // Byte Order (Endianness) 32-bit Swap.
157 def WriteBSWAP64 : SchedWrite; // Byte Order (Endianness) 64-bit Swap.
160 def WriteXCHG : SchedWrite; // Compare+Exchange - TODO RMW support.
172 defm WriteBSF : X86SchedWritePair; // Bit scan forward.
173 defm WriteBSR : X86SchedWritePair; // Bit scan reverse.
174 defm WritePOPCNT : X86SchedWritePair; // Bit population count.
183 def WriteBitTest : SchedWrite; // Bit Test
187 def WriteBitTestSet : SchedWrite; // Bit Test + Set
422 defm WriteCvtSD2I : X86SchedWritePair<ReadAfterVecLd>; // Double -> Integer.
423 defm WriteCvtPD2I : X86SchedWritePair<ReadAfterVecXLd>; // Double -> Integer (XMM).
424 defm WriteCvtPD2IY : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Integer (YMM).
425 defm WriteCvtPD2IZ : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Integer (ZMM).
427 defm WriteCvtSS2I : X86SchedWritePair<ReadAfterVecLd>; // Float -> Integer.
428 defm WriteCvtPS2I : X86SchedWritePair<ReadAfterVecXLd>; // Float -> Integer (XMM).
429 defm WriteCvtPS2IY : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Integer (YMM).
430 defm WriteCvtPS2IZ : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Integer (ZMM).
432 defm WriteCvtI2SD : X86SchedWritePair<ReadAfterVecLd>; // Integer -> Double.
433 defm WriteCvtI2PD : X86SchedWritePair<ReadAfterVecXLd>; // Integer -> Double (XMM).
434 defm WriteCvtI2PDY : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Double (YMM).
435 defm WriteCvtI2PDZ : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Double (ZMM).
437 defm WriteCvtI2SS : X86SchedWritePair<ReadAfterVecLd>; // Integer -> Float.
438 defm WriteCvtI2PS : X86SchedWritePair<ReadAfterVecXLd>; // Integer -> Float (XMM).
439 defm WriteCvtI2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Float (YMM).
440 defm WriteCvtI2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Integer -> Float (ZMM).
442 defm WriteCvtSS2SD : X86SchedWritePair<ReadAfterVecLd>; // Float -> Double size conversion.
443 defm WriteCvtPS2PD : X86SchedWritePair<ReadAfterVecXLd>; // Float -> Double size conversion (XMM).
444 defm WriteCvtPS2PDY : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Double size conversion (YMM).
445 defm WriteCvtPS2PDZ : X86SchedWritePair<ReadAfterVecYLd>; // Float -> Double size conversion (ZMM).
447 defm WriteCvtSD2SS : X86SchedWritePair<ReadAfterVecLd>; // Double -> Float size conversion.
448 defm WriteCvtPD2PS : X86SchedWritePair<ReadAfterVecXLd>; // Double -> Float size conversion (XMM).
449 defm WriteCvtPD2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Float size conversion (YMM).
450 defm WriteCvtPD2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Double -> Float size conversion (ZMM).
452 defm WriteCvtPH2PS : X86SchedWritePair<ReadAfterVecXLd>; // Half -> Float size conversion.
453 defm WriteCvtPH2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Half -> Float size conversion (YMM).
454 defm WriteCvtPH2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Half -> Float size conversion (ZMM).
456 def WriteCvtPS2PH : SchedWrite; // // Float -> Half size conversion.
457 def WriteCvtPS2PHY : SchedWrite; // // Float -> Half size conversion (YMM).
458 def WriteCvtPS2PHZ : SchedWrite; // // Float -> Half size conversion (ZMM).
459 def WriteCvtPS2PHSt : SchedWrite; // // Float -> Half + store size conversion.
460 def WriteCvtPS2PHYSt : SchedWrite; // // Float -> Half + store size conversion (YMM).
461 def WriteCvtPS2PHZSt : SchedWrite; // // Float -> Half + store size conversion (ZMM).
481 // Carry-less multiplication instructions.
491 // Catch-all for expensive system instructions.
495 defm WriteFShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // Fp 256-bit width vector shuffles.
496 defm WriteFVarShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // Fp 256-bit width variable shuffles.
497 defm WriteShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // 256-bit width vector shuffles.
498 defm WriteVPMOV256 : X86SchedWritePair<ReadAfterVecYLd>; // 256-bit width packed vector width-changing move.
499 defm WriteVarShuffle256 : X86SchedWritePair<ReadAfterVecYLd>; // 256-bit width vector variable shuffles.
717 //===----------------------------------------------------------------------===//
722 // Resources beyond the decoder operate on micro-ops and are bufferred
723 // so adjacent micro-ops don't directly compete.
727 // number of in-flight instructions.