Lines Matching full:src1
244 def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1 GR8:$src1)>;
245 def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1 GR16:$src1)>;
246 def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1 GR32:$src1)>;
247 def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1 GR64:$src1)>;
248 def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1 GR8:$src1)>;
249 def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1 GR16:$src1)>;
250 def : Pat<(rotr GR32:$src1, (i8 31)), (ROL32r1 GR32:$src1)>;
251 def : Pat<(rotr GR64:$src1, (i8 63)), (ROL64r1 GR64:$src1)>;
254 def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1_ND GR8:$src1)>;
255 def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1_ND GR16:$src1)>;
256 def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1_ND GR32:$src1)>;
257 def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1_ND GR64:$src1)>;
258 def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1_ND GR8:$src1)>;
259 def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1_ND GR16:$src1)>;
260 def : Pat<(rotr GR32:$src1, (i8 31)), (ROL32r1_ND GR32:$src1)>;
261 def : Pat<(rotr GR64:$src1, (i8 63)), (ROL64r1_ND GR64:$src1)>;
304 def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)),
305 (ROL8ri GR8:$src1, relocImm:$src2)>;
306 def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)),
307 (ROL16ri GR16:$src1, relocImm:$src2)>;
308 def : Pat<(rotl GR32:$src1, (i8 relocImm:$src2)),
309 (ROL32ri GR32:$src1, relocImm:$src2)>;
310 def : Pat<(rotl GR64:$src1, (i8 relocImm:$src2)),
311 (ROL64ri GR64:$src1, relocImm:$src2)>;
313 def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)),
314 (ROR8ri GR8:$src1, relocImm:$src2)>;
315 def : Pat<(rotr GR16:$src1, (i8 relocImm:$src2)),
316 (ROR16ri GR16:$src1, relocImm:$src2)>;
317 def : Pat<(rotr GR32:$src1, (i8 relocImm:$src2)),
318 (ROR32ri GR32:$src1, relocImm:$src2)>;
319 def : Pat<(rotr GR64:$src1, (i8 relocImm:$src2)),
320 (ROR64ri GR64:$src1, relocImm:$src2)>;
323 def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)),
324 (ROL8ri_ND GR8:$src1, relocImm:$src2)>;
325 def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)),
326 (ROL16ri_ND GR16:$src1, relocImm:$src2)>;
327 def : Pat<(rotl GR32:$src1, (i8 relocImm:$src2)),
328 (ROL32ri_ND GR32:$src1, relocImm:$src2)>;
329 def : Pat<(rotl GR64:$src1, (i8 relocImm:$src2)),
330 (ROL64ri_ND GR64:$src1, relocImm:$src2)>;
332 def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)),
333 (ROR8ri_ND GR8:$src1, relocImm:$src2)>;
334 def : Pat<(rotr GR16:$src1, (i8 relocImm:$src2)),
335 (ROR16ri_ND GR16:$src1, relocImm:$src2)>;
336 def : Pat<(rotr GR32:$src1, (i8 relocImm:$src2)),
337 (ROR32ri_ND GR32:$src1, relocImm:$src2)>;
338 def : Pat<(rotr GR64:$src1, (i8 relocImm:$src2)),
339 (ROR64ri_ND GR64:$src1, relocImm:$src2)>;
348 (ins t.RegClass:$src1, t.RegClass:$src2, u8imm:$src3), m, !if(!eq(ndd, 0), triop_args, triop_ndd_args),
354 [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, (i8 imm:$src3)))],
355 [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, (i8 imm:$src3)))]);
363 [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, CL))],
364 [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, CL))]);
368 : ITy<o, MRMDestMem, t, (outs), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
375 [(store (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)), addr:$src1)],
376 [(store (node t.RegClass:$src2, (t.LoadNode addr:$src1), (i8 imm:$src3)), addr:$src1)]);
385 [(store (node (t.LoadNode addr:$src1), t.RegClass:$src2, CL), addr:$src1)],
386 [(store (node t.RegClass:$src2, (t.LoadNode addr:$src1), CL), addr:$src1)]);
390 : ITy<o, MRMDestMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
396 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)))],
397 [(set t.RegClass:$dst, (node t.RegClass:$src2, (t.LoadNode addr:$src1), (i8 imm:$src3)))]);
405 [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1), t.RegClass:$src2, CL))],
406 [(set t.RegClass:$dst, (node t.RegClass:$src2, (t.LoadNode addr:$src1), CL))]);
509 Constraints = "$src1 = $dst" in {
511 (ins GR32:$src1, u8imm:$shamt), "",
512 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$shamt)))]>;
514 (ins GR64:$src1, u8imm:$shamt), "",
515 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$shamt)))]>;
518 (ins GR32:$src1, u8imm:$shamt), "",
519 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$shamt)))]>;
521 (ins GR64:$src1, u8imm:$shamt), "",
522 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$shamt)))]>;
542 : ITy<0xF0, MRMSrcReg, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, u8imm:$src2),
547 : ITy<0xF0, MRMSrcMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, u8imm:$src2),
568 : ITy<0xF7, MRMSrcReg4VOp3, t, (outs t.RegClass:$dst), (ins t.RegClass:$src1, t.RegClass:$src2),
572 : ITy<0xF7, MRMSrcMem4VOp3, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2),
575 // x86memop:$src1
642 def : Pat<(op GR32:$src1, GR8:$src2),
643 (!cast<Instruction>(NAME#"32rr"#suffix) GR32:$src1,
645 def : Pat<(op GR64:$src1, GR8:$src2),
646 (!cast<Instruction>(NAME#"64rr"#suffix) GR64:$src1,
648 def : Pat<(op GR32:$src1, (shiftMask32 GR8:$src2)),
649 (!cast<Instruction>(NAME#"32rr"#suffix) GR32:$src1,
651 def : Pat<(op GR64:$src1, (shiftMask64 GR8:$src2)),
652 (!cast<Instruction>(NAME#"64rr"#suffix) GR64:$src1,
665 def : Pat<(op (loadi32 addr:$src1), GR8:$src2),
666 (!cast<Instruction>(NAME#"32rm"#suffix) addr:$src1,
668 def : Pat<(op (loadi64 addr:$src1), GR8:$src2),
669 (!cast<Instruction>(NAME#"64rm"#suffix) addr:$src1,
671 def : Pat<(op (loadi32 addr:$src1), (shiftMask32 GR8:$src2)),
672 (!cast<Instruction>(NAME#"32rm"#suffix) addr:$src1,
674 def : Pat<(op (loadi64 addr:$src1), (shiftMask64 GR8:$src2)),
675 (!cast<Instruction>(NAME#"64rm"#suffix) addr:$src1,