Lines Matching +full:0 +full:xbe

3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
13 let hasSideEffects = 0 in {
15   def CBW : I<0x98, RawFrm, (outs), (ins),
18   def CWDE : I<0x98, RawFrm, (outs), (ins),
21   def CDQE : RI<0x98, RawFrm, (outs), (ins),
27   def CWD : I<0x99, RawFrm, (outs), (ins),
30   def CDQ : I<0x99, RawFrm, (outs), (ins),
33   def CQO  : RI<0x99, RawFrm, (outs), (ins),
38 let hasSideEffects = 0 in {
39 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
43 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
46 } // hasSideEffects = 0
47 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
51 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
55 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
59 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
64 let hasSideEffects = 0 in {
65 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
69 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
72 } // hasSideEffects = 0
73 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
77 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
81 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
85 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
93 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
94 def MOVSX16rr16: I<0xBF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
97 def MOVZX16rr16: I<0xB7, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
101 def MOVSX16rm16: I<0xBF, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
104 def MOVZX16rm16: I<0xB7, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
108 } // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0
113 let hasSideEffects = 0, isCodeGenOnly = 1 in {
114 def MOVZX32rr8_NOREX : I<0xB6, MRMSrcReg,
119 def MOVZX32rm8_NOREX : I<0xB6, MRMSrcMem,
124 def MOVSX32rr8_NOREX : I<0xBE, MRMSrcReg,
129 def MOVSX32rm8_NOREX : I<0xBE, MRMSrcMem,
139 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
143 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
147 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
151 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
155 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
159 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
167 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
168 def MOVSX16rr32: I<0x63, MRMSrcReg, (outs GR16:$dst), (ins GR32:$src),
171 def MOVSX32rr32: I<0x63, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
175 def MOVSX16rm32: I<0x63, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src),
178 def MOVSX32rm32: I<0x63, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
182 } // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0
185 let hasSideEffects = 0 in {
186 def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
190 def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
193 def MOVZX64rr16 : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
197 def MOVZX64rm16 : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
205           (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>;
207           (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
210           (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>;
212           (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
220           (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>;
222           (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;