Lines Matching full:src1
137 // ($src1) is already tied to $dst so we just use that for the preserved
139 // $src1.
149 !con((ins _.RC:$src1), NonTiedIns),
150 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
151 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
154 (Select _.KRCWM:$mask, RHS, _.RC:$src1),
167 !con((ins InVT.RC:$src1), NonTiedIns),
168 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
169 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
172 (bitconvert InVT.RC:$src1)),
203 !con((ins _.RC:$src1), NonTiedIns),
204 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
205 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
279 (vselect_mask _.KRCWM:$mask, MaskingRHS, _.RC:$src1))],
372 (ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
374 "$src3, $src2, $src1", "$src1, $src2, $src3",
375 (vinsert_insert:$src3 (To.VT To.RC:$src1),
378 (vinsert_for_mask:$src3 (To.VT To.RC:$src1),
384 (ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
386 "$src3, $src2, $src1", "$src1, $src2, $src3",
387 (vinsert_insert:$src3 (To.VT To.RC:$src1),
390 (vinsert_for_mask:$src3 (To.VT To.RC:$src1),
410 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
412 To.RC:$src1, From.RC:$src2,
416 (To.VT To.RC:$src1),
420 To.RC:$src1, addr:$src2,
528 (vinsert_insert:$ins (To.VT To.RC:$src1),
533 Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
538 (vinsert_insert:$ins (To.VT To.RC:$src1),
545 Cast.RC:$src0, Cast.KRCWM:$mask, To.RC:$src1, addr:$src2,
551 (vinsert_insert:$ins (To.VT To.RC:$src1),
556 Cast.KRCWM:$mask, To.RC:$src1, From.RC:$src2,
561 (vinsert_insert:$ins (To.VT To.RC:$src1),
566 Cast.KRCWM:$mask, To.RC:$src1, addr:$src2,
653 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
654 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
655 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, timm:$src3))]>,
658 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
659 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
660 [(set VR128X:$dst, (X86insertps VR128X:$src1,
681 (ins From.RC:$src1, u8imm:$idx),
683 "$idx, $src1", "$src1, $idx",
684 (vextract_extract:$idx (From.VT From.RC:$src1), (iPTR imm)),
685 (vextract_for_mask:$idx (From.VT From.RC:$src1), (iPTR imm))>,
689 (ins To.MemOp:$dst, From.RC:$src1, u8imm:$idx),
691 "\t{$idx, $src1, $dst|$dst, $src1, $idx}",
693 (From.VT From.RC:$src1), (iPTR imm))),
700 From.RC:$src1, u8imm:$idx),
702 "\t{$idx, $src1, $dst {${mask}}|"
703 "$dst {${mask}}, $src1, $idx}", []>,
720 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
722 From.RC:$src1,
724 def : Pat<(store (To.VT (vextract_extract:$ext (From.VT From.RC:$src1),
726 (!cast<Instruction>(InstrStr#"mr") addr:$dst, From.RC:$src1,
1002 (ins VR128X:$src1, u8imm:$src2),
1003 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1004 [(set GR32orGR64:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
1008 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
1009 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1010 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
1613 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain,
1618 (_.VT (X86VPermt2 _.RC:$src2, IdxVT.RC:$src1, _.RC:$src3)), 1>,
1625 (_.VT (X86VPermt2 _.RC:$src2, IdxVT.RC:$src1,
1634 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain,
1641 IdxVT.RC:$src1,(_.VT (_.BroadcastLdFrag addr:$src3)))), 1>,
1705 (CastVT.VT _.RC:$src1))),
1707 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1708 (!cast<Instruction>(InstrStr#"rrk") _.RC:$src1, _.KRCWM:$mask,
1713 (CastVT.VT _.RC:$src1))),
1715 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1716 (!cast<Instruction>(InstrStr#"rmk") _.RC:$src1, _.KRCWM:$mask,
1720 (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))),
1722 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1723 (!cast<Instruction>(InstrStr#"rmbk") _.RC:$src1, _.KRCWM:$mask,
1736 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
1740 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3)), 1>,
1746 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2,
1754 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
1759 (_.VT (X86VPermt2 _.RC:$src1,
1823 (ins _.RC:$src1, _.RC:$src2),
1825 "\t{$src2, $src1, ${dst}|${dst}, $src1, $src2}"), []>,
1828 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1830 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1833 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1835 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1839 (ins _.RC:$src1, _.MemOp:$src2),
1841 "\t{$src2, $src1, ${dst}|${dst}, $src1, $src2}"),
1845 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1847 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1851 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1853 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1863 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1865 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1866 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"), []>,
1871 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1873 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}} {z}|",
1874 "$dst {${mask}} {z}, $src1, ${src2}", _.BroadcastStr, "}"), []>,
1879 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1881 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1882 "$dst, $src1, ${src2}", _.BroadcastStr, "}"), []>,
1942 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1944 "$cc, $src2, $src1", "$src1, $src2, $cc",
1945 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc),
1946 (OpNode_su (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc)>,
1951 (ins _.RC:$src1, _.IntScalarMemOp:$src2, u8imm:$cc),
1953 "$cc, $src2, $src1", "$src1, $src2, $cc",
1954 (OpNode (_.VT _.RC:$src1), (_.ScalarIntMemFrags addr:$src2),
1956 … (OpNode_su (_.VT _.RC:$src1), (_.ScalarIntMemFrags addr:$src2),
1963 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1965 "$cc, {sae}, $src2, $src1","$src1, $src2, {sae}, $cc",
1966 (OpNodeSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1968 (OpNodeSAE_su (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1975 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, u8imm:$cc),
1977 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1978 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1984 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1986 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1987 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
2015 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
2016 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2020 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
2021 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2025 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
2026 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
2027 "$dst {${mask}}, $src1, $src2}"),
2031 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
2032 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
2033 "$dst {${mask}}, $src1, $src2}"),
2043 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
2044 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
2045 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
2048 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
2051 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
2052 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
2133 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
2135 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
2136 [(set _.KRC:$dst, (_.KVT (Frag:$cc (_.VT _.RC:$src1),
2141 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
2143 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
2146 (_.VT _.RC:$src1),
2152 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
2155 "\t{$cc, $src2, $src1, $dst {${mask}}|",
2156 "$dst {${mask}}, $src1, $src2, $cc}"),
2158 (_.KVT (Frag_su:$cc (_.VT _.RC:$src1),
2163 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
2166 "\t{$cc, $src2, $src1, $dst {${mask}}|",
2167 "$dst {${mask}}, $src1, $src2, $cc}"),
2171 (_.VT _.RC:$src1),
2177 (_.VT _.RC:$src1), cond)),
2179 _.RC:$src1, addr:$src2, (X86pcmpm_imm_commute $cc))>;
2183 (_.VT _.RC:$src1), cond))),
2185 _.KRCWM:$mask, _.RC:$src1, addr:$src2,
2194 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
2197 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
2198 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
2200 (_.VT _.RC:$src1),
2205 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
2208 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
2209 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
2212 (_.VT _.RC:$src1),
2218 (_.VT _.RC:$src1), cond)),
2220 _.RC:$src1, addr:$src2, (X86pcmpm_imm_commute $cc))>;
2224 (_.VT _.RC:$src1), cond))),
2226 _.KRCWM:$mask, _.RC:$src1, addr:$src2,
2293 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,u8imm:$cc),
2295 "$cc, $src2, $src1", "$src1, $src2, $cc",
2296 (X86any_cmpm (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc),
2297 (X86cmpm_su (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc),
2301 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
2303 "$cc, $src2, $src1", "$src1, $src2, $cc",
2304 (X86any_cmpm (_.VT _.RC:$src1), (_.VT (_.LdFrag addr:$src2)),
2306 (X86cmpm_su (_.VT _.RC:$src1), (_.VT (_.LdFrag addr:$src2)),
2312 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
2314 "$cc, ${src2}"#_.BroadcastStr#", $src1",
2315 "$src1, ${src2}"#_.BroadcastStr#", $cc",
2316 (X86any_cmpm (_.VT _.RC:$src1),
2319 (X86cmpm_su (_.VT _.RC:$src1),
2326 def : Pat<(X86any_cmpm (_.LdFrag addr:$src2), (_.VT _.RC:$src1),
2328 (!cast<Instruction>(Name#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2,
2332 (_.VT _.RC:$src1),
2335 _.RC:$src1, addr:$src2,
2339 (_.VT _.RC:$src1), timm:$cc),
2340 (!cast<Instruction>(Name#_.ZSuffix#"rmbi") _.RC:$src1, addr:$src2,
2344 (_.VT _.RC:$src1),
2347 _.RC:$src1, addr:$src2,
2351 def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc,
2353 (!cast<Instruction>(Name#_.ZSuffix#"rri") _.RC:$src1, _.RC:$src2, timm:$cc)>;
2355 def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc, _.KRCWM:$mask),
2356 (!cast<Instruction>(Name#_.ZSuffix#"rrik") _.KRCWM:$mask, _.RC:$src1,
2359 def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT (_.LdFrag addr:$src2)), timm:$cc,
2361 (!cast<Instruction>(Name#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2, timm:$cc)>;
2363 def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT (_.LdFrag addr:$src2)), timm:$cc,
2365 (!cast<Instruction>(Name#_.ZSuffix#"rmik") _.KRCWM:$mask, _.RC:$src1,
2368 def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT (_.BroadcastLdFrag addr:$src2)), timm:$cc,
2370 (!cast<Instruction>(Name#_.ZSuffix#"rmbi") _.RC:$src1, addr:$src2, timm:$cc)>;
2372 def : Pat<(X86cmpmm (_.VT _.RC:$src1), (_.VT (_.BroadcastLdFrag addr:$src2)), timm:$cc,
2374 (!cast<Instruction>(Name#_.ZSuffix#"rmbik") _.KRCWM:$mask, _.RC:$src1,
2378 def : Pat<(X86cmpmm (_.VT (_.LdFrag addr:$src2)), (_.VT _.RC:$src1), timm:$cc,
2380 (!cast<Instruction>(Name#_.ZSuffix#"rmi") _.RC:$src1, addr:$src2,
2383 def : Pat<(X86cmpmm (_.VT (_.LdFrag addr:$src2)), (_.VT _.RC:$src1), timm:$cc,
2386 _.RC:$src1, addr:$src2,
2389 def : Pat<(X86cmpmm (_.VT (_.BroadcastLdFrag addr:$src2)), (_.VT _.RC:$src1), timm:$cc,
2391 (!cast<Instruction>(Name#_.ZSuffix#"rmbi") _.RC:$src1, addr:$src2,
2394 def : Pat<(X86cmpmm (_.VT (_.BroadcastLdFrag addr:$src2)), (_.VT _.RC:$src1), timm:$cc,
2397 _.RC:$src1, addr:$src2,
2405 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
2406 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2, u8imm:$cc),
2408 "$cc, {sae}, $src2, $src1",
2409 "$src1, $src2, {sae}, $cc",
2410 [(set _.KRC:$dst, (X86cmpmmSAE (_.VT _.RC:$src1),
2412 [(set _.KRC:$dst, (X86cmpmmSAE (_.VT _.RC:$src1),
2439 def : Pat<(v1i1 (X86cmpms (loadf64 addr:$src2), FR64X:$src1, timm:$cc)),
2440 (VCMPSDZrmi FR64X:$src1, addr:$src2, (X86cmpm_imm_commute timm:$cc))>;
2442 def : Pat<(v1i1 (X86cmpms (loadf32 addr:$src2), FR32X:$src1, timm:$cc)),
2443 (VCMPSSZrmi FR32X:$src1, addr:$src2, (X86cmpm_imm_commute timm:$cc))>;
2447 def : Pat<(v1i1 (X86cmpms (loadf16 addr:$src2), FR16X:$src1, timm:$cc)),
2448 (VCMPSHZrmi FR16X:$src1, addr:$src2, (X86cmpm_imm_commute timm:$cc))>;
2461 (ins _.RC:$src1, i32u8imm:$src2),
2462 OpcodeStr#_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2463 [(set _.KRC:$dst,(X86Vfpclasss (_.VT _.RC:$src1),
2467 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
2469 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
2471 (X86Vfpclasss_su (_.VT _.RC:$src1),
2475 (ins _.IntScalarMemOp:$src1, i32u8imm:$src2),
2477 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2479 (X86Vfpclasss (_.ScalarIntMemFrags addr:$src1),
2483 (ins _.KRCWM:$mask, _.IntScalarMemOp:$src1, i32u8imm:$src2),
2485 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
2487 (X86Vfpclasss_su (_.ScalarIntMemFrags addr:$src1),
2501 (ins _.RC:$src1, i32u8imm:$src2),
2502 OpcodeStr#_.Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2503 [(set _.KRC:$dst,(X86Vfpclass (_.VT _.RC:$src1),
2507 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
2509 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
2511 (X86Vfpclass_su (_.VT _.RC:$src1),
2515 (ins _.MemOp:$src1, i32u8imm:$src2),
2517 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2519 (_.VT (_.LdFrag addr:$src1)),
2523 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
2525 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
2527 (_.VT (_.LdFrag addr:$src1)),
2531 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
2532 OpcodeStr#_.Suffix#"\t{$src2, ${src1}"#
2533 _.BroadcastStr#", $dst|$dst, ${src1}"
2536 (_.VT (_.BroadcastLdFrag addr:$src1)),
2540 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
2541 OpcodeStr#_.Suffix#"\t{$src2, ${src1}"#
2542 _.BroadcastStr#", $dst {${mask}}|$dst {${mask}}, ${src1}"#
2545 (_.VT (_.BroadcastLdFrag addr:$src1)),
2553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2555 _.KRC:$dst, _.RC:$src1, i32u8imm:$src2), 0, "att">;
2557 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
2559 _.KRC:$dst, _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2), 0, "att">;
2561 "\t{$src2, ${src1}"#_.BroadcastStr#", $dst|$dst, ${src1}"#
2564 _.KRC:$dst, _.ScalarMemOp:$src1, i32u8imm:$src2), 0, "att">;
2566 "\t{$src2, ${src1}"#_.BroadcastStr#", $dst {${mask}}|"
2567 "$dst {${mask}}, ${src1}"#_.BroadcastStr#", $src2}",
2569 _.KRC:$dst, _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2), 0, "att">;
2826 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2828 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2829 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>,
2860 def : Pat<(VOpNode VK8:$src1, VK8:$src2),
2862 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2866 def : Pat<(VOpNode VK1:$src1, VK1:$src2),
2868 (COPY_TO_REGCLASS VK1:$src1, VK16),
2870 def : Pat<(VOpNode VK2:$src1, VK2:$src2),
2872 (COPY_TO_REGCLASS VK2:$src1, VK16),
2874 def : Pat<(VOpNode VK4:$src1, VK4:$src2),
2876 (COPY_TO_REGCLASS VK4:$src1, VK16),
2893 (ins Src.KRC:$src1, Src.KRC:$src2),
2894 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2897 def : Pat<(Dst.KVT (concat_vectors Src.KRC:$src1, Src.KRC:$src2)),
2898 (!cast<Instruction>(NAME#rr) Src.KRC:$src2, Src.KRC:$src1)>;
2911 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2912 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2913 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>,
2968 def : Pat<(Narrow.KVT (Frag:$cc (Narrow.VT Narrow.RC:$src1),
2972 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
2977 (Narrow.KVT (Frag_su:$cc (Narrow.VT Narrow.RC:$src1),
2982 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
2992 def : Pat<(Narrow.KVT (Frag:$cc (Narrow.VT Narrow.RC:$src1),
2996 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3001 (Frag_su:$cc (Narrow.VT Narrow.RC:$src1),
3006 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3011 (Narrow.VT Narrow.RC:$src1),
3015 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3021 (Narrow.VT Narrow.RC:$src1),
3025 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3033 def : Pat<(Narrow.KVT (X86cmpm (Narrow.VT Narrow.RC:$src1),
3037 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3042 (X86cmpm_su (Narrow.VT Narrow.RC:$src1),
3046 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3051 def : Pat<(Narrow.KVT (X86cmpm (Narrow.VT Narrow.RC:$src1),
3055 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3059 (X86cmpm_su (Narrow.VT Narrow.RC:$src1),
3063 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3068 (Narrow.VT Narrow.RC:$src1), timm:$cc)),
3071 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3076 (Narrow.VT Narrow.RC:$src1), timm:$cc))),
3079 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
3226 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
3227 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
3228 "${dst} {${mask}}, $src1}"),
3230 (_.VT _.RC:$src1),
3234 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
3235 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
3236 "${dst} {${mask}}, $src1}"),
3239 (_.VT (ld_frag addr:$src1)),
3487 Narrow.RC:$src1, Narrow.RC:$src0)),
3493 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)))),
3497 Narrow.RC:$src1, Narrow.ImmAllZerosV)),
3502 (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)))),
3672 …def : Pat<(_.info512.VT (vselect VK32WM:$mask, (_.info512.VT VR512:$src1), (_.info512.VT VR512:$sr…
3673 (VMOVDQU16Zrrk VR512:$src0, VK32WM:$mask, VR512:$src1)>;
3674 …def : Pat<(_.info512.VT (vselect VK32WM:$mask, (_.info512.VT VR512:$src1), _.info512.ImmAllZerosV)…
3675 (VMOVDQU16Zrrkz VK32WM:$mask, VR512:$src1)>;
3699 …def : Pat<(_.info256.VT (vselect VK16WM:$mask, (_.info256.VT VR256X:$src1), (_.info256.VT VR256X:$…
3700 (VMOVDQU16Z256rrk VR256X:$src0, VK16WM:$mask, VR256X:$src1)>;
3701 …def : Pat<(_.info256.VT (vselect VK16WM:$mask, (_.info256.VT VR256X:$src1), _.info256.ImmAllZerosV…
3702 (VMOVDQU16Z256rrkz VK16WM:$mask, VR256X:$src1)>;
3725 …def : Pat<(_.info128.VT (vselect VK8WM:$mask, (_.info128.VT VR128X:$src1), (_.info128.VT VR128X:$s…
3726 (VMOVDQU16Z128rrk VR128X:$src0, VK8WM:$mask, VR128X:$src1)>;
3727 …def : Pat<(_.info128.VT (vselect VK8WM:$mask, (_.info128.VT VR128X:$src1), _.info128.ImmAllZerosV)…
3728 (VMOVDQU16Z128rrkz VK8WM:$mask, VR128X:$src1)>;
3901 (ins _.RC:$src1, _.RC:$src2),
3902 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3903 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2)))],
3907 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
3908 !strconcat(asm, "\t{$src2, $src1, $dst {${mask}} {z}|",
3909 "$dst {${mask}} {z}, $src1, $src2}"),
3911 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3916 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
3917 !strconcat(asm, "\t{$src2, $src1, $dst {${mask}}|",
3918 "$dst {${mask}}, $src1, $src2}"),
3920 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3976 (_.EltVT _.FRC:$src1),
3982 (_.VT (COPY_TO_REGCLASS _.FRC:$src1, _.RC)))>;
3987 (_.EltVT _.FRC:$src1),
3992 (_.VT (COPY_TO_REGCLASS _.FRC:$src1, _.RC)))>;
4173 def : Pat<(f16 (X86selects VK1WM:$mask, (f16 FR16X:$src1), (f16 FR16X:$src2))),
4177 (v8f16 (COPY_TO_REGCLASS FR16X:$src1, VR128X)))), FR16X)>;
4179 def : Pat<(f16 (X86selects VK1WM:$mask, (f16 FR16X:$src1), fp16imm0)),
4181 (v8f16 (COPY_TO_REGCLASS FR16X:$src1, VR128X)))), FR16X)>;
4241 def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
4245 (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)))), FR32X)>;
4247 def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), fp32imm0)),
4249 (v4f32 (COPY_TO_REGCLASS FR32X:$src1, VR128X)))), FR32X)>;
4259 def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
4263 (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)))), FR64X)>;
4265 def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), fp64imm0)),
4267 (v2f64 (COPY_TO_REGCLASS FR64X:$src1, VR128X)))), FR64X)>;
4278 def : Pat<(v4f32 (X86selects VK1WM:$mask, (v4f32 VR128X:$src1), (v4f32 VR128X:$src2))),
4279 (VMOVSSZrrk VR128X:$src2, VK1WM:$mask, VR128X:$src1, VR128X:$src1)>;
4280 def : Pat<(v2f64 (X86selects VK1WM:$mask, (v2f64 VR128X:$src1), (v2f64 VR128X:$src2))),
4281 (VMOVSDZrrk VR128X:$src2, VK1WM:$mask, VR128X:$src1, VR128X:$src1)>;
4283 def : Pat<(v4f32 (X86selects VK1WM:$mask, (v4f32 VR128X:$src1), (v4f32 immAllZerosV))),
4284 (VMOVSSZrrkz VK1WM:$mask, VR128X:$src1, VR128X:$src1)>;
4285 def : Pat<(v2f64 (X86selects VK1WM:$mask, (v2f64 VR128X:$src1), (v2f64 immAllZerosV))),
4286 (VMOVSDZrrkz VK1WM:$mask, VR128X:$src1, VR128X:$src1)>;
4291 (ins VR128X:$src1, VR128X:$src2),
4292 "vmovsh\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4299 VR128X:$src1, VR128X:$src2),
4300 "vmovsh\t{$src2, $src1, $dst {${mask}}|"#
4301 "$dst {${mask}}, $src1, $src2}",
4306 (ins f16x_info.KRCWM:$mask, VR128X:$src1, VR128X:$src2),
4307 "vmovsh\t{$src2, $src1, $dst {${mask}} {z}|"#
4308 "$dst {${mask}} {z}, $src1, $src2}",
4313 (ins VR128X:$src1, VR128X:$src2),
4314 "vmovss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4321 VR128X:$src1, VR128X:$src2),
4322 "vmovss\t{$src2, $src1, $dst {${mask}}|"#
4323 "$dst {${mask}}, $src1, $src2}",
4328 (ins f32x_info.KRCWM:$mask, VR128X:$src1, VR128X:$src2),
4329 "vmovss\t{$src2, $src1, $dst {${mask}} {z}|"#
4330 "$dst {${mask}} {z}, $src1, $src2}",
4335 (ins VR128X:$src1, VR128X:$src2),
4336 "vmovsd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4343 VR128X:$src1, VR128X:$src2),
4344 "vmovsd\t{$src2, $src1, $dst {${mask}}|"#
4345 "$dst {${mask}}, $src1, $src2}",
4350 (ins f64x_info.KRCWM:$mask, VR128X:$src1,
4352 "vmovsd\t{$src2, $src1, $dst {${mask}} {z}|"#
4353 "$dst {${mask}} {z}, $src1, $src2}",
4358 def : InstAlias<"vmovsh.s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4359 (VMOVSHZrr_REV VR128X:$dst, VR128X:$src1, VR128X:$src2), 0>;
4360 def : InstAlias<"vmovsh.s\t{$src2, $src1, $dst {${mask}}|"#
4361 "$dst {${mask}}, $src1, $src2}",
4363 VR128X:$src1, VR128X:$src2), 0>;
4364 def : InstAlias<"vmovsh.s\t{$src2, $src1, $dst {${mask}} {z}|"#
4365 "$dst {${mask}} {z}, $src1, $src2}",
4367 VR128X:$src1, VR128X:$src2), 0>;
4368 def : InstAlias<"vmovss.s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4369 (VMOVSSZrr_REV VR128X:$dst, VR128X:$src1, VR128X:$src2), 0>;
4370 def : InstAlias<"vmovss.s\t{$src2, $src1, $dst {${mask}}|"#
4371 "$dst {${mask}}, $src1, $src2}",
4373 VR128X:$src1, VR128X:$src2), 0>;
4374 def : InstAlias<"vmovss.s\t{$src2, $src1, $dst {${mask}} {z}|"#
4375 "$dst {${mask}} {z}, $src1, $src2}",
4377 VR128X:$src1, VR128X:$src2), 0>;
4378 def : InstAlias<"vmovsd.s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4379 (VMOVSDZrr_REV VR128X:$dst, VR128X:$src1, VR128X:$src2), 0>;
4380 def : InstAlias<"vmovsd.s\t{$src2, $src1, $dst {${mask}}|"#
4381 "$dst {${mask}}, $src1, $src2}",
4383 VR128X:$src1, VR128X:$src2), 0>;
4384 def : InstAlias<"vmovsd.s\t{$src2, $src1, $dst {${mask}} {z}|"#
4385 "$dst {${mask}} {z}, $src1, $src2}",
4387 VR128X:$src1, VR128X:$src2), 0>;
4669 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4670 "$src2, $src1", "$src1, $src2",
4671 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
4676 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4677 "$src2, $src1", "$src1, $src2",
4678 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2)))>,
4688 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4689 "${src2}"#_.BroadcastStr#", $src1",
4690 "$src1, ${src2}"#_.BroadcastStr,
4691 (_.VT (OpNode _.RC:$src1,
4797 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4798 "$src2, $src1","$src1, $src2",
4800 (_Src.VT _Src.RC:$src1),
4805 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4806 "$src2, $src1", "$src1, $src2",
4807 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
4813 (ins _Src.RC:$src1, _Brdct.ScalarMemOp:$src2),
4815 "${src2}"#_Brdct.BroadcastStr#", $src1",
4816 "$src1, ${src2}"#_Brdct.BroadcastStr,
4817 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
4884 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
4886 "${src2}"#_Src.BroadcastStr#", $src1",
4887 "$src1, ${src2}"#_Src.BroadcastStr,
4888 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
4899 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4900 "$src2, $src1","$src1, $src2",
4902 (_Src.VT _Src.RC:$src1),
4907 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4908 "$src2, $src1", "$src1, $src2",
4909 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
5015 def : Pat<(v4i64 (mul (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))),
5018 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
5021 def : Pat<(v4i64 (mul (v4i64 VR256X:$src1), (v4i64 (X86VBroadcastld64 addr:$src2)))),
5024 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
5028 def : Pat<(v2i64 (mul (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))),
5031 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
5034 def : Pat<(v2i64 (mul (v2i64 VR128X:$src1), (v2i64 (X86VBroadcastld64 addr:$src2)))),
5037 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
5043 def : Pat<(v4i64 (OpNode VR256X:$src1, VR256X:$src2)),
5046 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
5049 def : Pat<(v4i64 (OpNode (v4i64 VR256X:$src1), (v4i64 (X86VBroadcastld64 addr:$src2)))),
5052 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
5056 def : Pat<(v2i64 (OpNode VR128X:$src1, VR128X:$src2)),
5059 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
5062 def : Pat<(v2i64 (OpNode (v2i64 VR128X:$src1), (v2i64 (X86VBroadcastld64 addr:$src2)))),
5065 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
5091 def : Pat<(v16i8 (and VR128X:$src1, VR128X:$src2)),
5092 (VPANDQZ128rr VR128X:$src1, VR128X:$src2)>;
5093 def : Pat<(v8i16 (and VR128X:$src1, VR128X:$src2)),
5094 (VPANDQZ128rr VR128X:$src1, VR128X:$src2)>;
5096 def : Pat<(v16i8 (or VR128X:$src1, VR128X:$src2)),
5097 (VPORQZ128rr VR128X:$src1, VR128X:$src2)>;
5098 def : Pat<(v8i16 (or VR128X:$src1, VR128X:$src2)),
5099 (VPORQZ128rr VR128X:$src1, VR128X:$src2)>;
5101 def : Pat<(v16i8 (xor VR128X:$src1, VR128X:$src2)),
5102 (VPXORQZ128rr VR128X:$src1, VR128X:$src2)>;
5103 def : Pat<(v8i16 (xor VR128X:$src1, VR128X:$src2)),
5104 (VPXORQZ128rr VR128X:$src1, VR128X:$src2)>;
5106 def : Pat<(v16i8 (X86andnp VR128X:$src1, VR128X:$src2)),
5107 (VPANDNQZ128rr VR128X:$src1, VR128X:$src2)>;
5108 def : Pat<(v8i16 (X86andnp VR128X:$src1, VR128X:$src2)),
5109 (VPANDNQZ128rr VR128X:$src1, VR128X:$src2)>;
5111 def : Pat<(and VR128X:$src1, (loadv16i8 addr:$src2)),
5112 (VPANDQZ128rm VR128X:$src1, addr:$src2)>;
5113 def : Pat<(and VR128X:$src1, (loadv8i16 addr:$src2)),
5114 (VPANDQZ128rm VR128X:$src1, addr:$src2)>;
5116 def : Pat<(or VR128X:$src1, (loadv16i8 addr:$src2)),
5117 (VPORQZ128rm VR128X:$src1, addr:$src2)>;
5118 def : Pat<(or VR128X:$src1, (loadv8i16 addr:$src2)),
5119 (VPORQZ128rm VR128X:$src1, addr:$src2)>;
5121 def : Pat<(xor VR128X:$src1, (loadv16i8 addr:$src2)),
5122 (VPXORQZ128rm VR128X:$src1, addr:$src2)>;
5123 def : Pat<(xor VR128X:$src1, (loadv8i16 addr:$src2)),
5124 (VPXORQZ128rm VR128X:$src1, addr:$src2)>;
5126 def : Pat<(X86andnp VR128X:$src1, (loadv16i8 addr:$src2)),
5127 (VPANDNQZ128rm VR128X:$src1, addr:$src2)>;
5128 def : Pat<(X86andnp VR128X:$src1, (loadv8i16 addr:$src2)),
5129 (VPANDNQZ128rm VR128X:$src1, addr:$src2)>;
5131 def : Pat<(v32i8 (and VR256X:$src1, VR256X:$src2)),
5132 (VPANDQZ256rr VR256X:$src1, VR256X:$src2)>;
5133 def : Pat<(v16i16 (and VR256X:$src1, VR256X:$src2)),
5134 (VPANDQZ256rr VR256X:$src1, VR256X:$src2)>;
5136 def : Pat<(v32i8 (or VR256X:$src1, VR256X:$src2)),
5137 (VPORQZ256rr VR256X:$src1, VR256X:$src2)>;
5138 def : Pat<(v16i16 (or VR256X:$src1, VR256X:$src2)),
5139 (VPORQZ256rr VR256X:$src1, VR256X:$src2)>;
5141 def : Pat<(v32i8 (xor VR256X:$src1, VR256X:$src2)),
5142 (VPXORQZ256rr VR256X:$src1, VR256X:$src2)>;
5143 def : Pat<(v16i16 (xor VR256X:$src1, VR256X:$src2)),
5144 (VPXORQZ256rr VR256X:$src1, VR256X:$src2)>;
5146 def : Pat<(v32i8 (X86andnp VR256X:$src1, VR256X:$src2)),
5147 (VPANDNQZ256rr VR256X:$src1, VR256X:$src2)>;
5148 def : Pat<(v16i16 (X86andnp VR256X:$src1, VR256X:$src2)),
5149 (VPANDNQZ256rr VR256X:$src1, VR256X:$src2)>;
5151 def : Pat<(and VR256X:$src1, (loadv32i8 addr:$src2)),
5152 (VPANDQZ256rm VR256X:$src1, addr:$src2)>;
5153 def : Pat<(and VR256X:$src1, (loadv16i16 addr:$src2)),
5154 (VPANDQZ256rm VR256X:$src1, addr:$src2)>;
5156 def : Pat<(or VR256X:$src1, (loadv32i8 addr:$src2)),
5157 (VPORQZ256rm VR256X:$src1, addr:$src2)>;
5158 def : Pat<(or VR256X:$src1, (loadv16i16 addr:$src2)),
5159 (VPORQZ256rm VR256X:$src1, addr:$src2)>;
5161 def : Pat<(xor VR256X:$src1, (loadv32i8 addr:$src2)),
5162 (VPXORQZ256rm VR256X:$src1, addr:$src2)>;
5163 def : Pat<(xor VR256X:$src1, (loadv16i16 addr:$src2)),
5164 (VPXORQZ256rm VR256X:$src1, addr:$src2)>;
5166 def : Pat<(X86andnp VR256X:$src1, (loadv32i8 addr:$src2)),
5167 (VPANDNQZ256rm VR256X:$src1, addr:$src2)>;
5168 def : Pat<(X86andnp VR256X:$src1, (loadv16i16 addr:$src2)),
5169 (VPANDNQZ256rm VR256X:$src1, addr:$src2)>;
5173 def : Pat<(v64i8 (and VR512:$src1, VR512:$src2)),
5174 (VPANDQZrr VR512:$src1, VR512:$src2)>;
5175 def : Pat<(v32i16 (and VR512:$src1, VR512:$src2)),
5176 (VPANDQZrr VR512:$src1, VR512:$src2)>;
5178 def : Pat<(v64i8 (or VR512:$src1, VR512:$src2)),
5179 (VPORQZrr VR512:$src1, VR512:$src2)>;
5180 def : Pat<(v32i16 (or VR512:$src1, VR512:$src2)),
5181 (VPORQZrr VR512:$src1, VR512:$src2)>;
5183 def : Pat<(v64i8 (xor VR512:$src1, VR512:$src2)),
5184 (VPXORQZrr VR512:$src1, VR512:$src2)>;
5185 def : Pat<(v32i16 (xor VR512:$src1, VR512:$src2)),
5186 (VPXORQZrr VR512:$src1, VR512:$src2)>;
5188 def : Pat<(v64i8 (X86andnp VR512:$src1, VR512:$src2)),
5189 (VPANDNQZrr VR512:$src1, VR512:$src2)>;
5190 def : Pat<(v32i16 (X86andnp VR512:$src1, VR512:$src2)),
5191 (VPANDNQZrr VR512:$src1, VR512:$src2)>;
5193 def : Pat<(and VR512:$src1, (loadv64i8 addr:$src2)),
5194 (VPANDQZrm VR512:$src1, addr:$src2)>;
5195 def : Pat<(and VR512:$src1, (loadv32i16 addr:$src2)),
5196 (VPANDQZrm VR512:$src1, addr:$src2)>;
5198 def : Pat<(or VR512:$src1, (loadv64i8 addr:$src2)),
5199 (VPORQZrm VR512:$src1, addr:$src2)>;
5200 def : Pat<(or VR512:$src1, (loadv32i16 addr:$src2)),
5201 (VPORQZrm VR512:$src1, addr:$src2)>;
5203 def : Pat<(xor VR512:$src1, (loadv64i8 addr:$src2)),
5204 (VPXORQZrm VR512:$src1, addr:$src2)>;
5205 def : Pat<(xor VR512:$src1, (loadv32i16 addr:$src2)),
5206 (VPXORQZrm VR512:$src1, addr:$src2)>;
5208 def : Pat<(X86andnp VR512:$src1, (loadv64i8 addr:$src2)),
5209 (VPANDNQZrm VR512:$src1, addr:$src2)>;
5210 def : Pat<(X86andnp VR512:$src1, (loadv32i16 addr:$src2)),
5211 (VPANDNQZrm VR512:$src1, addr:$src2)>;
5220 (bitconvert (IntInfo.VT (OpNode _.RC:$src1, _.RC:$src2))),
5223 _.RC:$src1, _.RC:$src2)>;
5226 (bitconvert (IntInfo.VT (OpNode _.RC:$src1, _.RC:$src2))),
5228 (!cast<Instruction>(InstrStr#rrkz) _.KRCWM:$mask, _.RC:$src1,
5233 (bitconvert (IntInfo.VT (OpNode _.RC:$src1,
5237 _.RC:$src1, addr:$src2)>;
5239 (bitconvert (IntInfo.VT (OpNode _.RC:$src1,
5242 (!cast<Instruction>(InstrStr#rmkz) _.KRCWM:$mask, _.RC:$src1,
5252 (IntInfo.VT (OpNode _.RC:$src1,
5256 _.RC:$src1, addr:$src2)>;
5259 (IntInfo.VT (OpNode _.RC:$src1,
5263 _.RC:$src1, addr:$src2)>;
5355 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5356 "$src2, $src1", "$src1, $src2",
5357 (_.VT (VecNode _.RC:$src1, _.RC:$src2))>,
5361 (ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
5362 "$src2, $src1", "$src1, $src2",
5363 (_.VT (VecNode _.RC:$src1,
5368 (ins _.FRC:$src1, _.FRC:$src2),
5369 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5370 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>,
5375 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5376 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5377 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
5388 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5389 "$rc, $src2, $src1", "$src1, $src2, $rc",
5390 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5399 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5400 "$src2, $src1", "$src1, $src2",
5401 (_.VT (VecNode _.RC:$src1, _.RC:$src2))>,
5405 (ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
5406 "$src2, $src1", "$src1, $src2",
5407 (_.VT (VecNode _.RC:$src1,
5414 (ins _.FRC:$src1, _.FRC:$src2),
5415 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5416 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>,
5421 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5422 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5423 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
5430 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5431 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5432 (SaeNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
5493 (ins _.FRC:$src1, _.FRC:$src2),
5494 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5495 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>,
5500 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5501 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5502 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
5544 (ins _.RC:$src1, _.RC:$src2), OpcodeStr#suffix,
5545 "$src2, $src1", "$src1, $src2",
5546 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
5547 (_.VT (MaskOpNode _.RC:$src1, _.RC:$src2)), ClobberConstraint,
5551 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr#suffix,
5552 "$src2, $src1", "$src1, $src2",
5553 (OpNode _.RC:$src1, (_.LdFrag addr:$src2)),
5554 (MaskOpNode _.RC:$src1, (_.LdFrag addr:$src2)),
5557 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr#suffix,
5558 "${src2}"#_.BroadcastStr#", $src1",
5559 "$src1, ${src2}"#_.BroadcastStr,
5560 (OpNode _.RC:$src1, (_.VT (_.BroadcastLdFrag addr:$src2))),
5561 (MaskOpNode _.RC:$src1, (_.VT (_.BroadcastLdFrag addr:$src2))),
5574 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr#suffix,
5575 "$rc, $src2, $src1", "$src1, $src2, $rc",
5576 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 timm:$rc))),
5586 (ins _.RC:$src1, _.RC:$src2), OpcodeStr#_.Suffix,
5587 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5588 (_.VT (OpNodeSAE _.RC:$src1, _.RC:$src2))>,
5723 (ins _.RC:$src1, _.RC:$src2), OpcodeStr#_.Suffix,
5724 "$src2, $src1", "$src1, $src2",
5725 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>,
5728 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr#_.Suffix,
5729 "$src2, $src1", "$src1, $src2",
5730 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>,
5733 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr#_.Suffix,
5734 "${src2}"#_.BroadcastStr#", $src1",
5735 "$src1, ${src2}"#_.BroadcastStr,
5736 (OpNode _.RC:$src1, (_.VT (_.BroadcastLdFrag addr:$src2)))>,
5745 (ins _.RC:$src1, _.RC:$src2), OpcodeStr#_.Suffix,
5746 "$src2, $src1", "$src1, $src2",
5747 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>,
5750 (ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr#_.Suffix,
5751 "$src2, $src1", "$src1, $src2",
5752 (OpNode _.RC:$src1, (_.ScalarIntMemFrags addr:$src2))>,
5813 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5814 "$src2, $src1", "$src1, $src2",
5819 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5820 "$src2, $src1", "$src1, $src2",
5831 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
5832 "${src2}"#_.BroadcastStr#", $src1",
5833 "$src1, ${src2}"#_.BroadcastStr,
5902 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
5903 "$src2, $src1", "$src1, $src2",
5904 (_.VT (OpNode _.RC:$src1, (i8 timm:$src2)))>,
5907 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
5908 "$src2, $src1", "$src1, $src2",
5909 (_.VT (OpNode (_.VT (_.LdFrag addr:$src1)),
5920 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
5921 "$src2, ${src1}"#_.BroadcastStr, "${src1}"#_.BroadcastStr#", $src2",
5922 (_.VT (OpNode (_.BroadcastLdFrag addr:$src1), (i8 timm:$src2)))>,
5932 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
5933 "$src2, $src1", "$src1, $src2",
5934 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2)))>,
5937 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
5938 "$src2, $src1", "$src1, $src2",
5939 (_.VT (OpNode _.RC:$src1, (SrcVT (load addr:$src2))))>,
6048 def : Pat<(v4i64 (X86vsra (v4i64 VR256X:$src1), (v2i64 VR128X:$src2))),
6051 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
6054 def : Pat<(v2i64 (X86vsra (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))),
6057 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
6060 def : Pat<(v4i64 (X86vsrai (v4i64 VR256X:$src1), (i8 timm:$src2))),
6063 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
6066 def : Pat<(v2i64 (X86vsrai (v2i64 VR128X:$src1), (i8 timm:$src2))),
6069 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
6081 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
6082 "$src2, $src1", "$src1, $src2",
6083 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2)))>,
6086 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
6087 "$src2, $src1", "$src1, $src2",
6088 (_.VT (OpNode _.RC:$src1,
6099 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
6100 "${src2}"#_.BroadcastStr#", $src1",
6101 "$src1, ${src2}"#_.BroadcastStr,
6102 (_.VT (OpNode _.RC:$src1, (_.VT (_.BroadcastLdFrag addr:$src2))))>,
6133 def : Pat<(_.info256.VT (OpNode (_.info256.VT _.info256.RC:$src1),
6137 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
6141 def : Pat<(_.info128.VT (OpNode (_.info128.VT _.info128.RC:$src1),
6145 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
6184 def : Pat<(v2i64 (rotl (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))),
6187 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
6190 def : Pat<(v4i64 (rotl (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))),
6193 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
6197 def : Pat<(v4i32 (rotl (v4i32 VR128X:$src1), (v4i32 VR128X:$src2))),
6200 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
6203 def : Pat<(v8i32 (rotl (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
6206 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
6210 def : Pat<(v2i64 (X86vrotli (v2i64 VR128X:$src1), (i8 timm:$src2))),
6213 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
6215 def : Pat<(v4i64 (X86vrotli (v4i64 VR256X:$src1), (i8 timm:$src2))),
6218 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
6221 def : Pat<(v4i32 (X86vrotli (v4i32 VR128X:$src1), (i8 timm:$src2))),
6224 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
6226 def : Pat<(v8i32 (X86vrotli (v8i32 VR256X:$src1), (i8 timm:$src2))),
6229 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
6235 def : Pat<(v2i64 (rotr (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))),
6238 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
6241 def : Pat<(v4i64 (rotr (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))),
6244 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
6248 def : Pat<(v4i32 (rotr (v4i32 VR128X:$src1), (v4i32 VR128X:$src2))),
6251 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
6254 def : Pat<(v8i32 (rotr (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
6257 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
6261 def : Pat<(v2i64 (X86vrotri (v2i64 VR128X:$src1), (i8 timm:$src2))),
6264 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
6266 def : Pat<(v4i64 (X86vrotri (v4i64 VR256X:$src1), (i8 timm:$src2))),
6269 (v8i64 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
6272 def : Pat<(v4i32 (X86vrotri (v4i32 VR128X:$src1), (i8 timm:$src2))),
6275 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR128X:$src1, sub_xmm)),
6277 def : Pat<(v8i32 (X86vrotri (v8i32 VR256X:$src1), (i8 timm:$src2))),
6280 (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src1, sub_ymm)),
6357 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
6358 "$src2, $src1", "$src1, $src2",
6359 (_.VT (OpNode _.RC:$src1,
6363 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
6364 "$src2, $src1", "$src1, $src2",
6366 _.RC:$src1,
6371 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
6372 "${src2}"#_.BroadcastStr#", $src1",
6373 "$src1, ${src2}"#_.BroadcastStr,
6375 _.RC:$src1,
6453 (ins VR128X:$src1, VR128X:$src2),
6454 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6455 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))]>,
6459 (ins VR128X:$src1, VR128X:$src2),
6460 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6461 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))]>,
6474 (ins _.RC:$src1, f64mem:$src2),
6476 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6478 (OpNode _.RC:$src1,
6497 def : Pat<(v2f64 (X86Unpckl VR128X:$src1, (X86vzload64 addr:$src2))),
6498 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
6501 def : Pat<(v2f64 (X86Movsd VR128X:$src1, (X86vzload64 addr:$src2))),
6502 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
6545 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0,
6550 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
6551 (_.VT (MaskOpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)), 1, 1>,
6557 (_.VT (OpNode _.RC:$src2, _.RC:$src1, (_.LdFrag addr:$src3))),
6558 (_.VT (MaskOpNode _.RC:$src2, _.RC:$src1, (_.LdFrag addr:$src3))), 1, 0>,
6567 _.RC:$src1,(_.VT (_.BroadcastLdFrag addr:$src3))),
6569 _.RC:$src1,(_.VT (_.BroadcastLdFrag addr:$src3))), 1, 0>,
6578 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0,
6583 (_.VT ( OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3, (i32 timm:$rc))),
6584 (_.VT ( OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3, (i32 timm:$rc))), 1, 1>,
6640 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0,
6646 (_.VT (MaskOpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), 1, 1>,
6652 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1)),
6653 (_.VT (MaskOpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1)), 1, 0>,
6663 _.RC:$src1)),
6666 _.RC:$src1)), 1, 0>, EVEX, VVVV, EVEX_B,
6675 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0,
6681 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 timm:$rc))),
6736 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0,
6742 (_.VT (MaskOpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)), 1, 1>,
6750 (_.VT (OpNode (_.LdFrag addr:$src3), _.RC:$src1, _.RC:$src2)),
6751 (_.VT (MaskOpNode (_.LdFrag addr:$src3), _.RC:$src1, _.RC:$src2)), 1, 0>,
6762 _.RC:$src1, _.RC:$src2)),
6764 _.RC:$src1, _.RC:$src2)), 1, 0>,
6773 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0,
6779 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2, (i32 timm:$rc))),
6834 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
6855 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
6860 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
6868 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3, AVX512RC:$rc),
6874 }// Constraints = "$src1 = $dst"
6884 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
6886 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
6888 (set _.FRC:$dst, (_.EltVT (OpNodeRnd _.FRC:$src2, _.FRC:$src1,
6893 _.FRC:$src1))),
6895 (_.ScalarLdFrag addr:$src3), _.FRC:$src1))),
6897 _.FRC:$src1, (i32 timm:$rc)))), 1>;
6902 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
6905 _.FRC:$src1, _.FRC:$src2))),
6906 (set _.FRC:$dst, (_.EltVT (OpNodeRnd _.FRC:$src1, _.FRC:$src3,
6939 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6941 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
6944 VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)),
6947 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6949 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
6951 VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)),
6954 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6956 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
6959 VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)),
6962 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6963 (Op (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
6966 VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)),
6969 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6971 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
6973 VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)),
6976 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6979 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
6981 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
6983 VR128X:$src1, VK1WM:$mask,
6987 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6990 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
6992 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
6994 VR128X:$src1, VK1WM:$mask,
6997 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
6999 (MaskedOp (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
7001 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
7003 VR128X:$src1, VK1WM:$mask,
7006 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7009 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))),
7010 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
7012 VR128X:$src1, VK1WM:$mask,
7016 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7019 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))),
7020 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
7022 VR128X:$src1, VK1WM:$mask,
7025 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7028 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
7032 VR128X:$src1, VK1WM:$mask,
7036 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7039 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))),
7042 VR128X:$src1, VK1WM:$mask,
7046 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7049 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
7053 VR128X:$src1, VK1WM:$mask,
7056 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7058 (MaskedOp (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
7062 VR128X:$src1, VK1WM:$mask,
7065 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7068 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))),
7071 VR128X:$src1, VK1WM:$mask,
7075 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7077 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
7080 VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)),
7083 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7085 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
7088 VR128X:$src1, (_.VT (COPY_TO_REGCLASS _.FRC:$src2, VR128X)),
7091 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7094 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
7096 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
7098 VR128X:$src1, VK1WM:$mask,
7102 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7105 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
7107 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0)))))))),
7109 VR128X:$src1, VK1WM:$mask,
7113 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7116 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
7120 VR128X:$src1, VK1WM:$mask,
7124 def : Pat<(_.VT (Move (_.VT VR128X:$src1), (_.VT (scalar_to_vector
7127 (_.EltVT (extractelt (_.VT VR128X:$src1), (iPTR 0))),
7131 VR128X:$src1, VK1WM:$mask,
7166 let Constraints = "$src1 = $dst" in {
7175 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), 1, 1>,
7181 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
7191 _.RC:$src1)>,
7196 } // Constraints = "$src1 = $dst"
7232 (ins DstVT.FRC:$src1, SrcRC:$src),
7233 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
7237 (ins DstVT.FRC:$src1, x86memop:$src),
7238 asm#"{"#mem#"}\t{$src, $src1, $dst|$dst, $src1, $src}", []>,
7242 (ins DstVT.RC:$src1, SrcRC:$src2),
7243 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7245 (OpNode (DstVT.VT DstVT.RC:$src1), SrcRC:$src2))]>,
7249 (ins DstVT.RC:$src1, x86memop:$src2),
7250 asm#"{"#mem#"}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7252 (OpNode (DstVT.VT DstVT.RC:$src1),
7256 def : InstAlias<"v"#asm#mem#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7258 DstVT.RC:$src1, SrcRC:$src2), 0, "att">;
7267 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
7269 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
7271 (OpNode (DstVT.VT DstVT.RC:$src1),
7275 def : InstAlias<"v"#asm#mem#"\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}",
7277 DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc), 0, "att">;
7307 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
7308 (VCVTSI2SSZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">;
7309 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
7310 (VCVTSI2SDZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">;
7346 def : InstAlias<"vcvtusi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
7347 (VCVTUSI2SSZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">;
7348 def : InstAlias<"vcvtusi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
7349 (VCVTUSI2SDZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">;
7629 (ins _.RC:$src1, _Src.RC:$src2), OpcodeStr,
7630 "$src2, $src1", "$src1, $src2",
7631 (_.VT (OpNode (_.VT _.RC:$src1),
7635 (ins _.RC:$src1, _Src.IntScalarMemOp:$src2), OpcodeStr,
7636 "$src2, $src1", "$src1, $src2",
7637 (_.VT (OpNode (_.VT _.RC:$src1),
7644 (ins _.FRC:$src1, _Src.FRC:$src2),
7645 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7649 (ins _.FRC:$src1, _Src.ScalarMemOp:$src2),
7650 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7661 (ins _.RC:$src1, _Src.RC:$src2), OpcodeStr,
7662 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
7663 (_.VT (OpNodeSAE (_.VT _.RC:$src1),
7674 (ins _.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
7675 "$rc, $src2, $src1", "$src1, $src2, $rc",
7676 (_.VT (OpNodeRnd (_.VT _.RC:$src1),
8976 (ins _src.RC:$src1, i32u8imm:$src2),
8977 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8979 (X86any_cvtps2ph (_src.VT _src.RC:$src1), (i32 timm:$src2)))]>,
8983 (ins _dest.RC:$src0, _src.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
8984 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
8986 (X86mcvtps2ph (_src.VT _src.RC:$src1), (i32 timm:$src2),
8990 (ins _src.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
8991 "vcvtps2ph\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}",
8993 (X86mcvtps2ph (_src.VT _src.RC:$src1), (i32 timm:$src2),
8998 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
8999 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
9002 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
9003 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}", []>,
9013 (ins _src.RC:$src1, i32u8imm:$src2),
9014 "vcvtps2ph\t{$src2, {sae}, $src1, $dst|$dst, $src1, {sae}, $src2}",
9016 (X86cvtps2phSAE (_src.VT _src.RC:$src1), (i32 timm:$src2)))]>,
9020 (ins _dest.RC:$src0, _src.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
9021 … "vcvtps2ph\t{$src2, {sae}, $src1, $dst {${mask}}|$dst {${mask}}, $src1, {sae}, $src2}",
9023 (X86mcvtps2phSAE (_src.VT _src.RC:$src1), (i32 timm:$src2),
9027 (ins _src.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
9028 … "vcvtps2ph\t{$src2, {sae}, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, {sae}, $src2}",
9030 (X86mcvtps2phSAE (_src.VT _src.RC:$src1), (i32 timm:$src2),
9042 def : Pat<(store (v16i16 (X86any_cvtps2ph VR512:$src1, timm:$src2)), addr:$dst),
9043 (VCVTPS2PHZmr addr:$dst, VR512:$src1, timm:$src2)>;
9055 (bc_v2f64 (v8i16 (X86any_cvtps2ph VR128X:$src1, timm:$src2))),
9057 (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, timm:$src2)>;
9059 (bc_v2i64 (v8i16 (X86any_cvtps2ph VR128X:$src1, timm:$src2))),
9061 (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, timm:$src2)>;
9062 def : Pat<(store (v8i16 (X86any_cvtps2ph VR256X:$src1, timm:$src2)), addr:$dst),
9063 (VCVTPS2PHZ256mr addr:$dst, VR256X:$src1, timm:$src2)>;
9071 def rrb: AVX512<opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),
9072 !strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"), []>,
9147 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
9148 "$src2, $src1", "$src1, $src2",
9149 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
9152 (ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
9153 "$src2, $src1", "$src1, $src2",
9154 (OpNode (_.VT _.RC:$src1),
9249 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
9250 "$src2, $src1", "$src1, $src2",
9251 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
9255 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
9256 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
9257 (OpNodeSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
9261 (ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
9262 "$src2, $src1", "$src1, $src2",
9263 (OpNode (_.VT _.RC:$src1), (_.ScalarIntMemFrags addr:$src2))>,
9272 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
9273 "$src2, $src1", "$src1, $src2",
9276 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
9277 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
9281 (ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
9282 "$src2, $src1", "$src1, $src2",
9532 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
9533 "$src2, $src1", "$src1, $src2",
9534 (X86fsqrts (_.VT _.RC:$src1),
9538 (ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
9539 "$src2, $src1", "$src1, $src2",
9540 (X86fsqrts (_.VT _.RC:$src1),
9545 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
9546 "$rc, $src2, $src1", "$src1, $src2, $rc",
9547 (X86fsqrtRnds (_.VT _.RC:$src1),
9554 (ins _.FRC:$src1, _.FRC:$src2),
9555 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
9559 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
9560 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
9597 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
9598 "$src3, $src2, $src1", "$src1, $src2, $src3",
9599 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
9605 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
9606 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
9607 (_.VT (X86RndScalesSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2),
9612 (ins _.RC:$src1, _.IntScalarMemOp:$src2, i32u8imm:$src3),
9614 "$src3, $src2, $src1", "$src1, $src2, $src3",
9615 (_.VT (X86RndScales _.RC:$src1,
9621 (ins _.FRC:$src1, _.FRC:$src2, i32u8imm:$src3),
9622 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
9627 (ins _.FRC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
9628 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
9634 def : Pat<(X86any_VRndScale _.FRC:$src1, timm:$src2),
9636 _.FRC:$src1, timm:$src2))>;
9640 def : Pat<(X86any_VRndScale (_.ScalarLdFrag addr:$src1), timm:$src2),
9642 addr:$src1, timm:$src2))>;
9666 def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects_mask Mask,
9670 _.VT:$dst, OutMask, _.VT:$src2, _.VT:$src1)>;
9672 def : Pat<(Move _.VT:$src1, (scalar_to_vector (X86selects_mask Mask,
9676 OutMask, _.VT:$src2, _.VT:$src1)>;
10258 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
10261 (ins _.RC:$src1, MaskRC:$mask, memop:$src2),
10516 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
10578 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
10583 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
10649 (ins _.RC:$src1, i32u8imm:$src2),
10650 OpcodeStr#_.Suffix, "$src2, $src1", "$src1, $src2",
10651 (OpNode (_.VT _.RC:$src1), (i32 timm:$src2)),
10652 (MaskOpNode (_.VT _.RC:$src1), (i32 timm:$src2))>,
10655 (ins _.MemOp:$src1, i32u8imm:$src2),
10656 OpcodeStr#_.Suffix, "$src2, $src1", "$src1, $src2",
10657 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
10659 (MaskOpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
10663 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
10664 OpcodeStr#_.Suffix, "$src2, ${src1}"#_.BroadcastStr,
10665 "${src1}"#_.BroadcastStr#", $src2",
10666 (OpNode (_.VT (_.BroadcastLdFrag addr:$src1)),
10668 (MaskOpNode (_.VT (_.BroadcastLdFrag addr:$src1)),
10680 (ins _.RC:$src1, i32u8imm:$src2),
10681 OpcodeStr#_.Suffix, "$src2, {sae}, $src1",
10682 "$src1, {sae}, $src2",
10683 (OpNode (_.VT _.RC:$src1),
10714 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
10715 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
10716 (OpNode (_.VT _.RC:$src1),
10721 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
10722 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
10723 (OpNode (_.VT _.RC:$src1),
10728 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
10729 OpcodeStr, "$src3, ${src2}"#_.BroadcastStr#", $src1",
10730 "$src1, ${src2}"#_.BroadcastStr#", $src3",
10731 (OpNode (_.VT _.RC:$src1),
10745 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
10746 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
10747 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
10752 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
10753 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
10754 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
10771 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
10772 OpcodeStr, "$src3, ${src2}"#_.BroadcastStr#", $src1",
10773 "$src1, ${src2}"#_.BroadcastStr#", $src3",
10774 (OpNode (_.VT _.RC:$src1),
10786 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
10787 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
10788 (OpNode (_.VT _.RC:$src1),
10793 (ins _.RC:$src1, _.IntScalarMemOp:$src2, i32u8imm:$src3),
10794 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
10795 (OpNode (_.VT _.RC:$src1),
10808 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
10809 OpcodeStr, "$src3, {sae}, $src2, $src1",
10810 "$src1, $src2, {sae}, $src3",
10811 (OpNode (_.VT _.RC:$src1),
10822 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
10823 OpcodeStr, "$src3, {sae}, $src2, $src1",
10824 "$src1, $src2, {sae}, $src3",
10825 (OpNode (_.VT _.RC:$src1),
10954 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
10955 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
10957 (CastInfo.VT (X86Shuf128 _.RC:$src1, _.RC:$src2,
10961 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
10962 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
10965 (CastInfo.VT (X86Shuf128 _.RC:$src1,
10970 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
10971 OpcodeStr, "$src3, ${src2}"#_.BroadcastStr#", $src1",
10972 "$src1, ${src2}"#_.BroadcastStr#", $src3",
10976 (X86Shuf128 _.RC:$src1,
11008 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
11009 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
11010 (_.VT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 timm:$src3)))>,
11013 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
11014 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
11015 (_.VT (X86VAlign _.RC:$src1,
11021 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
11022 OpcodeStr, "$src3, ${src2}"#_.BroadcastStr#", $src1",
11023 "$src1, ${src2}"#_.BroadcastStr#", $src3",
11024 (X86VAlign _.RC:$src1,
11073 (From.VT (OpNode From.RC:$src1, From.RC:$src2,
11077 To.RC:$src1, To.RC:$src2,
11082 (From.VT (OpNode From.RC:$src1, From.RC:$src2,
11086 To.RC:$src1, To.RC:$src2,
11091 (From.VT (OpNode From.RC:$src1,
11096 To.RC:$src1, addr:$src2,
11101 (From.VT (OpNode From.RC:$src1,
11106 To.RC:$src1, addr:$src2,
11115 def : Pat<(From.VT (OpNode From.RC:$src1,
11118 (!cast<Instruction>(OpcodeStr#"rmbi") To.RC:$src1, addr:$src2,
11123 (From.VT (OpNode From.RC:$src1,
11129 To.RC:$src1, addr:$src2,
11134 (From.VT (OpNode From.RC:$src1,
11140 To.RC:$src1, addr:$src2,
11178 (ins _.RC:$src1), OpcodeStr,
11179 "$src1", "$src1",
11180 (_.VT (OpNode (_.VT _.RC:$src1)))>, EVEX, AVX5128IBase,
11184 (ins _.MemOp:$src1), OpcodeStr,
11185 "$src1", "$src1",
11186 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1)))))>,
11196 (ins _.ScalarMemOp:$src1), OpcodeStr,
11197 "${src1}"#_.BroadcastStr,
11198 "${src1}"#_.BroadcastStr,
11199 (_.VT (OpNode (_.VT (_.BroadcastLdFrag addr:$src1))))>,
11283 def : Pat<(_.info256.VT (OpNode (_.info256.VT _.info256.RC:$src1))),
11287 _.info256.RC:$src1,
11291 def : Pat<(_.info128.VT (OpNode (_.info128.VT _.info128.RC:$src1))),
11295 _.info128.RC:$src1,
11427 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
11428 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
11429 [(store (_.EltVT (trunc (OpNode (_.VT _.RC:$src1), timm:$src2))),
11437 (ins _.RC:$src1, u8imm:$src2),
11438 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
11440 (X86pextrb (_.VT _.RC:$src1), timm:$src2))]>,
11450 (ins _.RC:$src1, u8imm:$src2),
11451 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
11453 (X86pextrw (_.VT _.RC:$src1), timm:$src2))]>,
11458 (ins _.RC:$src1, u8imm:$src2),
11459 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
11470 (ins _.RC:$src1, u8imm:$src2),
11471 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
11473 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
11477 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
11478 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
11479 [(store (extractelt (_.VT _.RC:$src1),
11495 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
11496 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
11498 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), immoperator:$src3)))]>,
11506 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
11507 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
11509 (OpNode _.RC:$src1, GR32orGR64:$src2, timm:$src3))]>, EVEX, VVVV,
11520 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
11521 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
11523 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
11539 def : Pat<(X86pinsrb VR128:$src1,
11542 (VPINSRBrr VR128:$src1, (i32 (COPY_TO_REGCLASS VK8:$src2, GR32)),
11547 def : Pat<(X86pinsrb VR128:$src1, (i32 (anyext (i8 GR8:$src2))), timm:$src3),
11548 (VPINSRBZrr VR128:$src1, (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
11550 def : Pat<(X86pinsrb VR128:$src1,
11553 (VPINSRBZrr VR128:$src1, (i32 (COPY_TO_REGCLASS VK8:$src2, GR32)),
11587 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
11588 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
11589 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 timm:$src2))))]>,
11592 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
11593 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
11595 (_.VT (bitconvert (_.LdFrag addr:$src1))),
11625 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
11626 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
11628 (OpNode (_src.VT _src.RC:$src1),
11632 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
11633 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
11635 (OpNode (_src.VT _src.RC:$src1),
11723 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
11727 (OpNode (_.VT _.RC:$src1),
11735 (OpNode (_.VT _.RC:$src1),
11745 (OpNode (_.VT _.RC:$src1),
11751 }// Constraints = "$src1 = $dst"
11755 (OpNode _.RC:$src3, _.RC:$src2, _.RC:$src1, (i8 timm:$src4)),
11756 _.RC:$src1)),
11757 (!cast<Instruction>(Name#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask,
11760 (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3, (i8 timm:$src4)),
11761 _.RC:$src1)),
11762 (!cast<Instruction>(Name#_.ZSuffix#rrik) _.RC:$src1, _.KRCWM:$mask,
11769 _.RC:$src2, _.RC:$src1, (i8 timm:$src4)),
11771 (!cast<Instruction>(Name#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask,
11774 (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)),
11777 (!cast<Instruction>(Name#_.ZSuffix#rmikz) _.RC:$src1, _.KRCWM:$mask,
11783 (OpNode _.RC:$src1, (bitconvert (_.LdFrag addr:$src3)),
11785 _.RC:$src1)),
11786 (!cast<Instruction>(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
11790 _.RC:$src2, _.RC:$src1, (i8 timm:$src4)),
11791 _.RC:$src1)),
11792 (!cast<Instruction>(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
11795 (OpNode _.RC:$src2, _.RC:$src1,
11797 _.RC:$src1)),
11798 (!cast<Instruction>(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
11802 _.RC:$src1, (i8 timm:$src4)),
11803 _.RC:$src1)),
11804 (!cast<Instruction>(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
11808 _.RC:$src1, _.RC:$src2, (i8 timm:$src4)),
11809 _.RC:$src1)),
11810 (!cast<Instruction>(Name#_.ZSuffix#rmik) _.RC:$src1, _.KRCWM:$mask,
11817 _.RC:$src2, _.RC:$src1, (i8 timm:$src4)),
11819 (!cast<Instruction>(Name#_.ZSuffix#rmbikz) _.RC:$src1,
11823 (OpNode _.RC:$src1,
11827 (!cast<Instruction>(Name#_.ZSuffix#rmbikz) _.RC:$src1,
11834 (OpNode _.RC:$src1, (_.BroadcastLdFrag addr:$src3),
11836 _.RC:$src1)),
11837 (!cast<Instruction>(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
11841 _.RC:$src2, _.RC:$src1, (i8 timm:$src4)),
11842 _.RC:$src1)),
11843 (!cast<Instruction>(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
11846 (OpNode _.RC:$src2, _.RC:$src1,
11848 (i8 timm:$src4)), _.RC:$src1)),
11849 (!cast<Instruction>(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
11854 _.RC:$src1, (i8 timm:$src4)),
11855 _.RC:$src1)),
11856 (!cast<Instruction>(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
11860 _.RC:$src1, _.RC:$src2, (i8 timm:$src4)),
11861 _.RC:$src1)),
11862 (!cast<Instruction>(Name#_.ZSuffix#rmbik) _.RC:$src1, _.KRCWM:$mask,
11988 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain,
11993 (X86VFixupimm (_.VT _.RC:$src1),
12000 (X86VFixupimm (_.VT _.RC:$src1),
12009 (X86VFixupimm (_.VT _.RC:$src1),
12014 } // Constraints = "$src1 = $dst"
12021 let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, Uses = [MXCSR] in {
12026 (X86VFixupimmSAE (_.VT _.RC:$src1),
12037 let Constraints = "$src1 = $dst" , Predicates = [HasAVX512],
12042 (X86VFixupimms (_.VT _.RC:$src1),
12051 (X86VFixupimmSAEs (_.VT _.RC:$src1),
12059 (X86VFixupimms (_.VT _.RC:$src1),
12158 def : Pat<(MoveNode (_.VT VR128X:$src1),
12162 (extractelt (_.VT VR128X:$src1), (iPTR 0))),
12167 VK1WM:$mask, _.VT:$src1,
12169 def : Pat<(MoveNode (_.VT VR128X:$src1),
12173 (extractelt (_.VT VR128X:$src1), (iPTR 0))),
12178 VK1WM:$mask, _.VT:$src1, addr:$src2)>;
12181 def : Pat<(MoveNode (_.VT VR128X:$src1),
12185 (extractelt (_.VT VR128X:$src1), (iPTR 0))),
12188 VK1WM:$mask, _.VT:$src1,
12190 def : Pat<(MoveNode (_.VT VR128X:$src1),
12194 (extractelt (_.VT VR128X:$src1), (iPTR 0))),
12196 (!cast<I>("V"#OpcPrefix#"Zrm_Intkz") VK1WM:$mask, _.VT:$src1, addr:$src2)>;
12283 let Constraints = "$src1 = $dst",
12288 (VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2, VTI.RC:$src3))>,
12293 (VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2,
12303 let Constraints = "$src1 = $dst",
12309 (OpNode VTI.RC:$src1, VTI.RC:$src2,
12382 let Constraints = "$src1 = $dst" in
12390 (VTI.VT (OpNode VTI.RC:$src1,
12397 (VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2,
12406 (OpNode VTI.RC:$src1, VTI.RC:$src2,
12435 def : Pat<(v16i32 (add VR512:$src1,
12437 (VPDPWSSDZr VR512:$src1, VR512:$src2, VR512:$src3)>;
12438 def : Pat<(v16i32 (add VR512:$src1,
12440 (VPDPWSSDZm VR512:$src1, VR512:$src2, addr:$src3)>;
12443 def : Pat<(v8i32 (add VR256X:$src1,
12445 (VPDPWSSDZ256r VR256X:$src1, VR256X:$src2, VR256X:$src3)>;
12446 def : Pat<(v8i32 (add VR256X:$src1,
12448 (VPDPWSSDZ256m VR256X:$src1, VR256X:$src2, addr:$src3)>;
12449 def : Pat<(v4i32 (add VR128X:$src1,
12451 (VPDPWSSDZ128r VR128X:$src1, VR128X:$src2, VR128X:$src3)>;
12452 def : Pat<(v4i32 (add VR128X:$src1,
12454 (VPDPWSSDZ128m VR128X:$src1, VR128X:$src2, addr:$src3)>;
12472 (ins VTI.RC:$src1, VTI.RC:$src2),
12474 "$src2, $src1", "$src1, $src2",
12475 (X86Vpshufbitqmb (VTI.VT VTI.RC:$src1),
12477 (X86Vpshufbitqmb_su (VTI.VT VTI.RC:$src1),
12481 (ins VTI.RC:$src1, VTI.MemOp:$src2),
12483 "$src2, $src1", "$src1, $src2",
12484 (X86Vpshufbitqmb (VTI.VT VTI.RC:$src1),
12486 (X86Vpshufbitqmb_su (VTI.VT VTI.RC:$src1),
12531 (ins VTI.RC:$src1, BcstVTI.ScalarMemOp:$src2, u8imm:$src3),
12532 OpStr, "$src3, ${src2}"#BcstVTI.BroadcastStr#", $src1",
12533 "$src1, ${src2}"#BcstVTI.BroadcastStr#", $src3",
12534 (OpNode (VTI.VT VTI.RC:$src1),
12566 Constraints = "$src1 = $dst", Uses = [MXCSR], mayRaiseFPException = 1 in {
12597 Constraints = "$src1 = $dst" in {
12625 (ins _.RC:$src1, _.RC:$src2),
12627 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
12629 _.RC:$src1, (_.VT _.RC:$src2)))]>,
12634 (ins _.RC:$src1, _.MemOp:$src2),
12636 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
12638 _.RC:$src1, (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
12644 (ins _.RC:$src1, _.ScalarMemOp:$src2),
12646 ", $src1, $dst|$dst, $src1, ${src2}", _.BroadcastStr ,"}"),
12648 _.RC:$src1, (_.VT (_.BroadcastLdFrag addr:$src2))))]>,
12808 let Constraints = "$src1 = $dst" in {
12815 (_.VT (OpNode _.RC:$src1, src_v.RC:$src2, src_v.RC:$src3))>,
12821 (_.VT (OpNode _.RC:$src1, src_v.RC:$src2,
12835 } // Constraints = "$src1 = $dst"
13271 def : InstAlias<"vcvtsi2sh\t{$src, $src1, $dst|$dst, $src1, $src}",
13272 (VCVTSI2SHZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">;
13274 def : InstAlias<"vcvtusi2sh\t{$src, $src1, $dst|$dst, $src1, $src}",
13275 (VCVTUSI2SHZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">;
13455 let Constraints = "@earlyclobber $dst, $src1 = $dst" in {
13460 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), IsCommutable>, EVEX, VVVV;
13465 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>, EVEX, VVVV;
13470 …(_.VT (OpNode _.RC:$src2, (_.VT (_.BroadcastLdFrag addr:$src3)), _.RC:$src1))>, EVEX_B, EVEX, VVVV;
13472 } // Constraints = "@earlyclobber $dst, $src1 = $dst"
13476 let Constraints = "@earlyclobber $dst, $src1 = $dst" in
13480 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 timm:$rc)))>,
13529 let Predicates = [HasFP16], Constraints = "@earlyclobber $dst, $src1 = $dst" in {
13533 (v4f32 (OpNode VR128X:$src2, VR128X:$src3, VR128X:$src1)), IsCommutable>,
13538 (v4f32 (OpNode VR128X:$src2, (sse_load_f32 addr:$src3), VR128X:$src1))>,
13543 … (v4f32 (OpNodeRnd VR128X:$src2, VR128X:$src3, VR128X:$src1, (i32 timm:$rc)))>,
13552 (ins VR128X:$src1, VR128X:$src2), OpcodeStr,
13553 "$src2, $src1", "$src1, $src2",
13554 (v4f32 (OpNode VR128X:$src1, VR128X:$src2)),
13558 (ins VR128X:$src1, ssmem:$src2), OpcodeStr,
13559 "$src2, $src1", "$src1, $src2",
13560 (v4f32 (OpNode VR128X:$src1, (sse_load_f32 addr:$src2))),
13564 (ins VR128X:$src1, VR128X:$src2, AVX512RC:$rc), OpcodeStr,
13565 "$rc, $src2, $src1", "$src1, $src2, $rc",
13566 (OpNodeRnd (v4f32 VR128X:$src1), (v4f32 VR128X:$src2), (i32 timm:$rc)),