Lines Matching full:ve
1 //===-- VEInstrInfo.cpp - VE Instruction Information ----------------------===//
9 // This file contains the VE implementation of the TargetInstrInfo class.
14 #include "VE.h"
28 #define DEBUG_TYPE "ve-instr-info"
39 : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {} in VEInstrInfo()
98 using namespace llvm::VE; in isUncondBranchOpcode()
101 // VE has other branch relative always instructions for word/double/float, in isUncondBranchOpcode()
113 using namespace llvm::VE; in isCondBranchOpcode()
125 using namespace llvm::VE; in isIndirectBranchOpcode()
129 // VE has other branch always instructions for word/double/float, but in isIndirectBranchOpcode()
233 "VE branch conditions should have three component!"); in insertBranch()
238 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
254 opc[0] = VE::BRCFWir; in insertBranch()
255 opc[1] = VE::BRCFWrr; in insertBranch()
257 opc[0] = VE::BRCFLir; in insertBranch()
258 opc[1] = VE::BRCFLrr; in insertBranch()
262 opc[0] = VE::BRCFSir; in insertBranch()
263 opc[1] = VE::BRCFSrr; in insertBranch()
265 opc[0] = VE::BRCFDir; in insertBranch()
266 opc[1] = VE::BRCFDrr; in insertBranch()
286 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
322 return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) || in IsAliasOfSX()
323 VE::F32RegClass.contains(Reg); in IsAliasOfSX()
339 if (MCID.getOpcode() == VE::ORri) { in copyPhysSubRegs()
344 } else if (MCID.getOpcode() == VE::ANDMmm) { in copyPhysSubRegs()
347 BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc); in copyPhysSubRegs()
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) in copyPhysReg()
368 } else if (VE::V64RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
376 Register TmpReg = VE::SX16; in copyPhysReg()
377 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32); in copyPhysReg()
378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) in copyPhysReg()
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) in copyPhysReg()
387 } else if (VE::VMRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) in copyPhysReg()
389 .addReg(VE::VM0) in copyPhysReg()
391 } else if (VE::VM512RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; in copyPhysReg()
395 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ANDMmm), in copyPhysReg()
397 } else if (VE::F128RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; in copyPhysReg()
401 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ORri), in copyPhysReg()
418 if (MI.getOpcode() == VE::LDrii || // I64 in isLoadFromStackSlot()
419 MI.getOpcode() == VE::LDLSXrii || // I32 in isLoadFromStackSlot()
420 MI.getOpcode() == VE::LDUrii || // F32 in isLoadFromStackSlot()
421 MI.getOpcode() == VE::LDQrii || // F128 (pseudo) in isLoadFromStackSlot()
422 MI.getOpcode() == VE::LDVMrii || // VM (pseudo) in isLoadFromStackSlot()
423 MI.getOpcode() == VE::LDVM512rii // VM512 (pseudo) in isLoadFromStackSlot()
442 if (MI.getOpcode() == VE::STrii || // I64 in isStoreToStackSlot()
443 MI.getOpcode() == VE::STLrii || // I32 in isStoreToStackSlot()
444 MI.getOpcode() == VE::STUrii || // F32 in isStoreToStackSlot()
445 MI.getOpcode() == VE::STQrii || // F128 (pseudo) in isStoreToStackSlot()
446 MI.getOpcode() == VE::STVMrii || // VM (pseudo) in isStoreToStackSlot()
447 MI.getOpcode() == VE::STVM512rii // VM512 (pseudo) in isStoreToStackSlot()
476 if (RC == &VE::I64RegClass) { in storeRegToStackSlot()
477 BuildMI(MBB, I, DL, get(VE::STrii)) in storeRegToStackSlot()
483 } else if (RC == &VE::I32RegClass) { in storeRegToStackSlot()
484 BuildMI(MBB, I, DL, get(VE::STLrii)) in storeRegToStackSlot()
490 } else if (RC == &VE::F32RegClass) { in storeRegToStackSlot()
491 BuildMI(MBB, I, DL, get(VE::STUrii)) in storeRegToStackSlot()
497 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
498 BuildMI(MBB, I, DL, get(VE::STQrii)) in storeRegToStackSlot()
504 } else if (RC == &VE::VMRegClass) { in storeRegToStackSlot()
505 BuildMI(MBB, I, DL, get(VE::STVMrii)) in storeRegToStackSlot()
511 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
512 BuildMI(MBB, I, DL, get(VE::STVM512rii)) in storeRegToStackSlot()
538 if (RC == &VE::I64RegClass) { in loadRegFromStackSlot()
539 BuildMI(MBB, I, DL, get(VE::LDrii), DestReg) in loadRegFromStackSlot()
544 } else if (RC == &VE::I32RegClass) { in loadRegFromStackSlot()
545 BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg) in loadRegFromStackSlot()
550 } else if (RC == &VE::F32RegClass) { in loadRegFromStackSlot()
551 BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg) in loadRegFromStackSlot()
556 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
557 BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg) in loadRegFromStackSlot()
562 } else if (RC == &VE::VMRegClass) { in loadRegFromStackSlot()
563 BuildMI(MBB, I, DL, get(VE::LDVMrii), DestReg) in loadRegFromStackSlot()
568 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
569 BuildMI(MBB, I, DL, get(VE::LDVM512rii), DestReg) in loadRegFromStackSlot()
587 case VE::ORim: in foldImmediate()
588 // General move small immediate instruction on VE. in foldImmediate()
598 case VE::LEAzii: in foldImmediate()
599 // General move immediate instruction on VE. in foldImmediate()
647 using namespace llvm::VE; in foldImmediate()
763 GlobalBaseReg = VE::SX15; in getGlobalBaseReg()
770 BuildMI(FirstMBB, MBBI, dl, get(VE::GETGOT), GlobalBaseReg); in getGlobalBaseReg()
776 return (reg - VE::VMP0) * 2 + VE::VM0; in getVM512Upper()
799 case VE::NEGMy: in expandPseudoLogM()
847 {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}}, in expandPseudoVFMK()
848 {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}}, in expandPseudoVFMK()
849 {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}}, in expandPseudoVFMK()
850 {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}}, in expandPseudoVFMK()
851 {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}}, in expandPseudoVFMK()
852 {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}}, in expandPseudoVFMK()
878 case VE::EXTEND_STACK: { in expandPostRAPseudo()
881 case VE::EXTEND_STACK_GUARD: { in expandPostRAPseudo()
885 case VE::GETSTACKTOP: { in expandPostRAPseudo()
889 case VE::ANDMyy: in expandPostRAPseudo()
890 expandPseudoLogM(MI, get(VE::ANDMmm)); in expandPostRAPseudo()
892 case VE::ORMyy: in expandPostRAPseudo()
893 expandPseudoLogM(MI, get(VE::ORMmm)); in expandPostRAPseudo()
895 case VE::XORMyy: in expandPostRAPseudo()
896 expandPseudoLogM(MI, get(VE::XORMmm)); in expandPostRAPseudo()
898 case VE::EQVMyy: in expandPostRAPseudo()
899 expandPseudoLogM(MI, get(VE::EQVMmm)); in expandPostRAPseudo()
901 case VE::NNDMyy: in expandPostRAPseudo()
902 expandPseudoLogM(MI, get(VE::NNDMmm)); in expandPostRAPseudo()
904 case VE::NEGMy: in expandPostRAPseudo()
905 expandPseudoLogM(MI, get(VE::NEGMm)); in expandPostRAPseudo()
908 case VE::LVMyir: in expandPostRAPseudo()
909 case VE::LVMyim: in expandPostRAPseudo()
910 case VE::LVMyir_y: in expandPostRAPseudo()
911 case VE::LVMyim_y: { in expandPostRAPseudo()
916 MI.getOpcode() == VE::LVMyir || MI.getOpcode() == VE::LVMyir_y; in expandPostRAPseudo()
917 Register Src = IsSrcReg ? MI.getOperand(2).getReg() : VE::NoRegister; in expandPostRAPseudo()
928 case VE::LVMyir: in expandPostRAPseudo()
929 BuildMI(*MBB, MI, DL, get(VE::LVMir)) in expandPostRAPseudo()
934 case VE::LVMyim: in expandPostRAPseudo()
935 BuildMI(*MBB, MI, DL, get(VE::LVMim)) in expandPostRAPseudo()
940 case VE::LVMyir_y: in expandPostRAPseudo()
943 BuildMI(*MBB, MI, DL, get(VE::LVMir_m)) in expandPostRAPseudo()
949 case VE::LVMyim_y: in expandPostRAPseudo()
952 BuildMI(*MBB, MI, DL, get(VE::LVMim_m)) in expandPostRAPseudo()
962 case VE::SVMyi: { in expandPostRAPseudo()
976 BuildMI(*MBB, MI, DL, get(VE::SVMmi), Dest).addReg(VMZ).addImm(Imm); in expandPostRAPseudo()
985 case VE::VFMKyal: in expandPostRAPseudo()
986 case VE::VFMKynal: in expandPostRAPseudo()
987 case VE::VFMKWyvl: in expandPostRAPseudo()
988 case VE::VFMKWyvyl: in expandPostRAPseudo()
989 case VE::VFMKSyvl: in expandPostRAPseudo()
990 case VE::VFMKSyvyl: in expandPostRAPseudo()
1037 BuildMI(BB, dl, TII.get(VE::BRCFLrr_t)) in expandExtendStackPseudo()
1039 .addReg(VE::SX11) // %sp in expandExtendStackPseudo()
1040 .addReg(VE::SX8) // %sl in expandExtendStackPseudo()
1048 BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61) in expandExtendStackPseudo()
1049 .addReg(VE::SX14) in expandExtendStackPseudo()
1052 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62) in expandExtendStackPseudo()
1053 .addReg(VE::SX0) in expandExtendStackPseudo()
1055 BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63) in expandExtendStackPseudo()
1059 BuildMI(BB, dl, TII.get(VE::SHMLri)) in expandExtendStackPseudo()
1060 .addReg(VE::SX61) in expandExtendStackPseudo()
1062 .addReg(VE::SX63); in expandExtendStackPseudo()
1063 BuildMI(BB, dl, TII.get(VE::SHMLri)) in expandExtendStackPseudo()
1064 .addReg(VE::SX61) in expandExtendStackPseudo()
1066 .addReg(VE::SX8); in expandExtendStackPseudo()
1067 BuildMI(BB, dl, TII.get(VE::SHMLri)) in expandExtendStackPseudo()
1068 .addReg(VE::SX61) in expandExtendStackPseudo()
1070 .addReg(VE::SX11); in expandExtendStackPseudo()
1071 BuildMI(BB, dl, TII.get(VE::MONC)); in expandExtendStackPseudo()
1073 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX0) in expandExtendStackPseudo()
1074 .addReg(VE::SX62) in expandExtendStackPseudo()
1095 // The VE ABI requires a reserved area at the top of stack as described in expandGetStackTopPseudo()
1103 BuildMI(*MBB, MI, DL, TII.get(VE::LEArii)) in expandGetStackTopPseudo()
1105 .addReg(VE::SX11) in expandGetStackTopPseudo()