Lines Matching full:ve
1 //===-- VEAsmParser.cpp - Parse VE assembly to MCInst instructions --------===//
12 #include "VE.h"
36 #define DEBUG_TYPE "ve-asmparser"
69 // Custom parse functions for VE specific operands.
102 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
103 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
104 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
105 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
106 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
107 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
108 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
109 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
110 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
111 VE::SW63};
114 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,
115 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,
116 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
117 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
118 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
119 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
120 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
121 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
122 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
123 VE::SF63};
126 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
127 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
128 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
129 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
131 static const MCPhysReg VM512Regs[8] = {VE::VMP0, VE::VMP1, VE::VMP2, VE::VMP3,
132 VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7};
135 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
136 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
137 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,
138 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
139 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,
140 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,
141 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,
142 VE::PMC12, VE::PMC13, VE::PMC14};
146 /// VEOperand - Instances of this class represent a parsed VE machine
162 // Other special cases for Aurora VE
647 unsigned regIdx = Reg - VE::SX0; in MorphToI32Reg()
656 unsigned regIdx = Reg - VE::SX0; in MorphToF32Reg()
665 unsigned regIdx = Reg - VE::SX0; in MorphToF128Reg()
674 unsigned regIdx = Reg - VE::VM0; in MorphToVM512Reg()
686 if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister) in MorphToMISCReg()
813 // GCC supports case insensitive register names. All of the VE registers in parseRegisterName()
815 if (RegNum == VE::NoRegister) { in parseRegisterName()
835 Reg = VE::NoRegister; in tryParseRegister()
841 if (Reg == VE::NoRegister) in tryParseRegister()
844 if (Reg != VE::NoRegister) { in tryParseRegister()
1006 // Defines VE specific directives. Reference is "Vector Engine Assembly in parseDirective()
1010 // The .word is 4 bytes long on VE. in parseDirective()
1014 // The .long is 8 bytes long on VE. in parseDirective()
1018 // The .llong is 8 bytes long on VE. in parseDirective()
1358 Operands.push_back(BaseReg != VE::NoRegister in parseMEMAsOperand()
1364 if (BaseReg != VE::NoRegister) in parseMEMAsOperand()
1390 Operands.push_back(BaseReg != VE::NoRegister in parseMEMAsOperand()
1560 // VE uses identical register name for all registers like both in validateTargetOperandClass()