1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
43   // Wraps a TargetGlobalAddress that should be loaded using PC-relative
58   // Floating-point comparisons.  The two operands are the values to compare.
69   // operand 1 is the 4-bit condition-code mask, with bit N in
70   // big-endian order meaning "branch if CC=N"; operand 2 is the
75   // mask of condition-code values for which operand 0 should be
81   // base of the dynamically-allocatable area.
104   // Operand 1 is a mask of all condition-code values that may result of this
105   // operation, operand 2 is a mask of condition-code values that may result
113   // - the target address
114   // - the source address
115   // - the constant length
133   // Use an MVST-based sequence to implement stpcpy().
136   // Use a CLST-based sequence to implement strcmp().  The two input operands
140   // Use an SRST-based sequence to search a block of memory.  The first
159   // 15-N of the single operand.
162   // Create a vector constant by replicating an element-sized RISBG-style mask.
178   // Interleave elements from the high half of operand 0 and the high half
191   // The third operand is a 4-bit value of the form 0A0B, where A and B
198   // in the same way as a byte-level VECTOR_SHUFFLE mask.
201   // Pack vector operands 0 and 1 into a single vector with half-sized elements.
209   // Unpack the first half of vector operand 0 into double-sized elements.
210   // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
225   // For each element of the output type, sum across all sub-elements of
227   // rightmost sub-element of the corresponding element of operand 1.
237   // Compare integer vector operands 0 and 1 to produce the usual 0/-1
249   // Compare floating-point vector operands 0 and 1 to produce the usual 0/-1
261   // Test floating-point data class for vectors.
275   // i128 high integer comparisons.
279   // String operations that set CC as a side-effect.
308   // Strict variants of scalar floating-point comparisons.
313   // Strict variants of vector floating-point comparisons.
326   // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
329   // Operand 0: the address of the containing 32-bit-aligned field
330   // Operand 1: the second operand of <op>, in the high bits of an i32
333   //            operand into the high bits
350   // Operand 0: the address of the containing 32-bit-aligned field
354   //            operand into the high bits
359   // Atomic compare-and-swap returning CC value.
363   // 128-bit atomic load.
367   // 128-bit atomic store.
371   // 128-bit atomic compare-and-swap.
384   // Prefetch from the second operand using the 4-bit control code in
390 // Return true if OPCODE is some kind of PC-relative address.
424   TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)  in getPreferredVectorAction()  argument
430     //     sub-128 vectors without having to handle them as legal types.  in getPreferredVectorAction()
437     if (VT.getScalarSizeInBits() % 8 == 0)  in getPreferredVectorAction()
439     return TargetLoweringBase::getPreferredVectorAction(VT);  in getPreferredVectorAction()
442   getNumRegisters(LLVMContext &Context, EVT VT,  in getNumRegisters()  argument
445     if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)  in getNumRegisters()
447     return TargetLowering::getNumRegisters(Context, VT);  in getNumRegisters()
450                                     EVT VT) const override {  in getRegisterTypeForCallingConv()  argument
451     // 128-bit single-element vector types are passed like other vectors,  in getRegisterTypeForCallingConv()
453     if (VT.isVector() && VT.getSizeInBits() == 128 &&  in getRegisterTypeForCallingConv()
454         VT.getVectorNumElements() == 1)  in getRegisterTypeForCallingConv()
456     return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);  in getRegisterTypeForCallingConv()
463     return Mask && Mask->getValue().isIntN(16);  in isMaskAndCmp0FoldingBeneficial()
465   bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {  in convertSetCCLogicToBitwiseLogic()  argument
466     return VT.isScalarInteger();  in convertSetCCLogicToBitwiseLogic()
471                                   EVT VT) const override;
472   bool isFPImmLegal(const APFloat &Imm, EVT VT,
474   bool ShouldShrinkFPConstant(EVT VT) const override {  in ShouldShrinkFPConstant()  argument
475     // Do not shrink 64-bit FP constpool entries since LDEB is slower than  in ShouldShrinkFPConstant()
477     return VT != MVT::f64;  in ShouldShrinkFPConstant()
489   bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment,
501   bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
505     return VT == MVT::i32 || VT == MVT::i64;
515                                StringRef Constraint, MVT VT) const override;
559   Register getRegisterByName(const char *RegName, LLT VT,
658                        const SDLoc &DL, EVT VT,
661                            EVT VT, ISD::CondCode CC,
714   SDValue buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
728   bool canTreatAsByteVector(EVT VT) const;
738   bool canLoadStoreByteSwapped(EVT VT) const;
758   // CCMask and Target are the BRC-like operands for the branch.
806   const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;