Lines Matching +full:co +full:- +full:processor

1 //===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
36 // Registers are identified with 5-bit ID numbers.
37 // Ri - 32-bit integer registers
40 // Rdi - pairs of 32-bit integer registers
46 // Rf - 32-bit floating-point registers
49 // Rd - Slots in the FP register file for 64-bit floating-point values.
56 // Rq - Slots in the FP register file for 128-bit floating-point values.
64 def ICC : SparcCtrlReg<0, "icc">; // This represents icc and xcc in 64-bit code.
65 foreach I = 0-3 in
68 def FSR  : SparcCtrlReg<0, "fsr">; // Floating-point state register.
69 def FQ   : SparcCtrlReg<0, "fq">;  // Floating-point deferred-trap queue.
70 def CPSR : SparcCtrlReg<0, "csr">; // Co-processor state register.
71 def CPQ  : SparcCtrlReg<0, "cq">;  // Co-processor queue.
81 // %asr2-asr6      : valid on both V8 and V9.
175 // Floating-point registers
209 // Aliases of the F* registers used to hold 64-bit fp values (doubles)
227 // Co-processor registers
280 // Aliases of the F* registers used to hold 128-bit for values (long doubles).
298 // Aliases of the integer registers used for LDD/STD double-word operations
316 // Aliases of the co-processor registers used for LDD/STD double-word operations
355 // Register class for 64-bit mode, with a 64-bit spill slot size.
356 // These are the same as the 32-bit registers, so TableGen will consider this
357 // to be a sub-class of IntRegs. That works out because requiring a 64-bit
358 // spill slot is a stricter constraint than only requiring a 32-bit spill slot.
366 // The Low?FPRegs classes are used only for inline-asm constraints.
379   // FIXME: TICK is special-cased here as it can be accessed