1 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
30 // clang-format off
37   /// Select with condition operator - This selects between a true value and
57   // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
60   // Multiply high for signedxunsigned.
68   // RV64I shifts, directly matching the semantics of the named RISC-V
73   // 32-bit operations from RV64M that can't be simply matched with a pattern
79   // RV64IB rotates, directly matching the semantics of the named RISC-V
84   // named RISC-V instructions.
91   // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
95   // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
96   // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
98   // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
101   // unnecessary GPR->FPR->GPR moves.
132   // Floating point fmax and fmin matching the RISC-V instruction semantics.
135   // A read of the 64-bit counter CSR on a 32-bit target (returns (Lo, Hi)).
137   // CSR numbers of the low and high parts of the counter).
153   // May-Be-Operations
177   // Splats an 64-bit value that has been split into two i32 parts. This is
181   // Truncates a RVV integer vector by one power-of-two. Carries both an extra
185   // pass-thru operand, the second is the source vector, the third is the XLenVT
186   // index (either constant or non-constant), the fourth is the mask, the fifth
204   // Matches the semantics of the vfcnvt.rod function (Convert double-width
205   // float to single-width float, rounding towards odd). Takes a double-width
206   // float vector and produces a single-width float vector. Also has a mask and
212   // third vector operand. The first operand is the pass-thru operand. The
214   // third operand's types are expected to be the corresponding full-width
408   CZERO_EQZ, // vt.maskc for XVentanaCondOps.
409   CZERO_NEZ, // vt.maskcn for XVentanaCondOps.
478 // clang-format on
523   std::pair<int, bool> getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
524   bool isFPImmLegal(const APFloat &Imm, EVT VT,
529   bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
538                                     EVT VT) const override;
544                                          EVT VT) const override;
547                                                 CallingConv::ID CC, EVT VT,
553                                             EVT VT) const override;
557   bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
561     // save two bitwise instructions and one float-to-int instruction and  in isMultiStoresCheaperThanBitsMerge()
563     // significant benefit because it avoids the float->int domain switch  in isMultiStoresCheaperThanBitsMerge()
576   shouldExpandBuildVectorWithShuffles(EVT VT,
579   bool shouldExpandCttzElements(EVT VT) const override;
582   InstructionCost getLMULCost(MVT VT) const;
584   InstructionCost getVRGatherVVCost(MVT VT) const;
585   InstructionCost getVRGatherVICost(MVT VT) const;
586   InstructionCost getVSlideVXCost(MVT VT) const;
587   InstructionCost getVSlideVICost(MVT VT) const;
638                                StringRef Constraint, MVT VT) const override;
652                          EVT VT) const override;
654   bool shouldFormOverflowOp(unsigned Opcode, EVT VT,  in shouldFormOverflowOp()  argument
656     if (VT == MVT::i8 || VT == MVT::i16)  in shouldFormOverflowOp()
659     return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);  in shouldFormOverflowOp()
669   bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {  in convertSetCCLogicToBitwiseLogic()  argument
670     return VT.isScalarInteger();  in convertSetCCLogicToBitwiseLogic()
672   bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }  in convertSelectOfConstantsToMath()  argument
674   bool isCtpopFast(EVT VT) const override;
676   unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override;
689                                   EVT VT) const override;
728   /// with the clang -ffixed-xX flag for access to be allowed.
729   Register getRegisterByName(const char *RegName, LLT VT,
755   bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
778       EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
798   static RISCVII::VLMUL getLMUL(MVT VT);
809   // Return inclusive (low, high) bounds on the value of VLMAX for the
815   static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
816   static unsigned getRegClassIDForVecVT(MVT VT);
821   MVT getContainerForFixedLengthVector(MVT VT) const;
827   bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
894   /// RISCVCCAssignFn - This target-specific function extends the default
895   /// CCValAssign with additional information used to lower RISC-V calling
1008   bool useRVVForFixedLengthVectorVT(MVT VT) const;
1021   bool mergeStoresAfterLegalization(EVT VT) const override;
1026   /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
1038   bool shouldFoldSelectWithSingleBitTest(EVT VT,
1051 /// the v8 register, if a vector register group between v8-v23 that has not been
1057 /// NFIELDS consecutive vector register groups between v8-v23 that have not been
1068     MVT VT;  member