Lines Matching refs:RBReg
1671 unsigned RBReg = SPReg; in emitEpilogue() local
1714 BuildMI(MBB, MBBI, dl, OrInst, RBReg). in emitEpilogue()
1725 RBReg = FPReg; in emitEpilogue()
1727 BuildMI(MBB, MBBI, dl, AddImmInst, RBReg) in emitEpilogue()
1732 .addReg(RBReg) in emitEpilogue()
1760 RBReg = FPReg; in emitEpilogue()
1762 BuildMI(MBB, StackUpdateLoc, dl, LoadInst, RBReg) in emitEpilogue()
1767 assert(RBReg != ScratchReg && "Should have avoided ScratchReg"); in emitEpilogue()
1791 if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) { in emitEpilogue()
1794 .addReg(RBReg); in emitEpilogue()
1799 assert(RBReg == SPReg && "Should be using SP as a base register"); in emitEpilogue()
1802 .addReg(RBReg); in emitEpilogue()
1808 if (HasRedZone || RBReg == SPReg) in emitEpilogue()
1815 .addReg(RBReg); in emitEpilogue()
1821 .addReg(RBReg); in emitEpilogue()
1826 .addReg(RBReg); in emitEpilogue()
1830 if (RBReg != SPReg || SPAdd != 0) { in emitEpilogue()
1835 .addReg(RBReg) in emitEpilogue()
1836 .addReg(RBReg); in emitEpilogue()
1839 .addReg(RBReg) in emitEpilogue()
1842 assert(RBReg != ScratchReg && "Should be using FP or SP as base register"); in emitEpilogue()
1843 if (RBReg == FPReg) in emitEpilogue()