Lines Matching +full:high +full:- +full:vt

1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
65       // Get the Highest (63-48) 16 bits from a 64-bit immediate
68       // Get the Higher (47-32) 16 bits from a 64-bit immediate
71       // Get the High 16 bits from a 32/64-bit immediate
75       // Get the Lower 16 bits from a 32/64-bit immediate
79       // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
82       // Get the High 16 bits from a 32-bit immediate for accessing TLS.
113       // FP-to-int truncation node.
227       SHF,   // 4-element set shuffle.
238       // Combined (XOR (OR $a, $b), -1)
245       // Double select nodes for machines without conditional-move.
262   //===--------------------------------------------------------------------===//
264   //===--------------------------------------------------------------------===//
276     /// createFastISel - This method returns a target specific FastISel object,
285     EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
297                                       EVT VT) const override;
303                                            EVT VT) const override;
307         LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
314       if (ArgTy->isVectorTy())  in getABIAlignmentForCallingConv()
323     /// LowerOperation - Provide custom lowering hooks for some operations.
326     /// ReplaceNodeResults - Replace the results of node with an illegal result
332     /// getTargetNodeName - This method returns the name of a target specific
336     /// getSetCCResultType - get the ISD::SETCC result ValueType
338                            EVT VT) const override;
351     Register getRegisterByName(const char* RegName, LLT VT,
412     // computing a global symbol's address in large-GOT mode:
429     // computing a symbol's address in non-PIC mode:
445    // computing a symbol's address in non-PIC mode for N64.
447    // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
475     // computing a symbol's address using gp-relative addressing:
563     /// isEligibleForTailCallOptimization - Check whether the call is eligible
570     /// copyByValArg - Copy argument registers which were used to pass a byval
581     /// passByValArg - Pass a byval argument in registers or on stack.
590     /// writeVarArgRegs - Write variable function arguments passed in registers
633     /// This function parses registers that appear in inline-asm constraints.
636     parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
640                                  StringRef Constraint, MVT VT) const override;
642     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
670     /// isFPImmLegal - Returns true if the target can instruction select the
673     bool isFPImmLegal(const APFloat &Imm, EVT VT,
683     /// Emit a sign-extension using sll/sra, seb, or seh appropriately.