Lines Matching full:decoder
84 const MCDisassembler *Decoder);
88 const MCDisassembler *Decoder);
92 const MCDisassembler *Decoder);
96 const MCDisassembler *Decoder);
100 const MCDisassembler *Decoder);
104 const MCDisassembler *Decoder);
108 const MCDisassembler *Decoder);
112 const MCDisassembler *Decoder);
116 const MCDisassembler *Decoder);
120 const MCDisassembler *Decoder);
124 const MCDisassembler *Decoder);
128 const MCDisassembler *Decoder);
132 const MCDisassembler *Decoder);
136 const MCDisassembler *Decoder);
140 const MCDisassembler *Decoder);
144 const MCDisassembler *Decoder);
148 const MCDisassembler *Decoder);
152 const MCDisassembler *Decoder);
156 const MCDisassembler *Decoder);
160 const MCDisassembler *Decoder);
164 const MCDisassembler *Decoder);
168 const MCDisassembler *Decoder);
172 const MCDisassembler *Decoder);
176 const MCDisassembler *Decoder);
180 const MCDisassembler *Decoder);
184 const MCDisassembler *Decoder);
188 const MCDisassembler *Decoder);
192 const MCDisassembler *Decoder);
196 const MCDisassembler *Decoder);
200 const MCDisassembler *Decoder);
204 const MCDisassembler *Decoder);
210 const MCDisassembler *Decoder);
216 const MCDisassembler *Decoder);
222 const MCDisassembler *Decoder);
228 const MCDisassembler *Decoder);
234 const MCDisassembler *Decoder);
240 const MCDisassembler *Decoder);
243 const MCDisassembler *Decoder);
246 const MCDisassembler *Decoder);
250 const MCDisassembler *Decoder);
253 const MCDisassembler *Decoder);
257 const MCDisassembler *Decoder);
261 const MCDisassembler *Decoder);
265 const MCDisassembler *Decoder);
268 const MCDisassembler *Decoder);
272 const MCDisassembler *Decoder);
275 const MCDisassembler *Decoder);
279 const MCDisassembler *Decoder);
283 const MCDisassembler *Decoder);
287 const MCDisassembler *Decoder);
291 const MCDisassembler *Decoder);
295 const MCDisassembler *Decoder);
299 const MCDisassembler *Decoder);
303 const MCDisassembler *Decoder);
307 const MCDisassembler *Decoder);
310 const MCDisassembler *Decoder);
314 const MCDisassembler *Decoder);
317 const MCDisassembler *Decoder);
320 const MCDisassembler *Decoder);
324 const MCDisassembler *Decoder);
328 const MCDisassembler *Decoder);
332 const MCDisassembler *Decoder);
336 const MCDisassembler *Decoder);
340 const MCDisassembler *Decoder);
344 const MCDisassembler *Decoder);
349 const MCDisassembler *Decoder);
354 const MCDisassembler *Decoder) { in DecodeUImmWithOffset() argument
356 Decoder); in DecodeUImmWithOffset()
362 const MCDisassembler *Decoder);
365 const MCDisassembler *Decoder);
369 const MCDisassembler *Decoder);
373 const MCDisassembler *Decoder);
376 const MCDisassembler *Decoder);
380 const MCDisassembler *Decoder);
384 const MCDisassembler *Decoder);
386 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
390 const MCDisassembler *Decoder);
395 const MCDisassembler *Decoder);
399 const MCDisassembler *Decoder);
404 const MCDisassembler *Decoder);
409 const MCDisassembler *Decoder);
414 const MCDisassembler *Decoder);
419 const MCDisassembler *Decoder);
424 const MCDisassembler *Decoder);
429 const MCDisassembler *Decoder);
434 const MCDisassembler *Decoder);
439 const MCDisassembler *Decoder);
444 const MCDisassembler *Decoder);
449 const MCDisassembler *Decoder);
454 const MCDisassembler *Decoder);
459 const MCDisassembler *Decoder);
463 const MCDisassembler *Decoder);
467 const MCDisassembler *Decoder);
471 const MCDisassembler *Decoder);
475 const MCDisassembler *Decoder);
479 const MCDisassembler *Decoder);
483 const MCDisassembler *Decoder);
487 const MCDisassembler *Decoder);
491 const MCDisassembler *Decoder);
528 const MCDisassembler *Decoder) { in DecodeINSVE_DF() argument
556 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
559 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
566 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
577 const MCDisassembler *Decoder) { in DecodeDAHIDATIMMR6() argument
580 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
591 const MCDisassembler *Decoder) { in DecodeDAHIDATI() argument
594 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
596 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
606 const MCDisassembler *Decoder) { in DecodeAddiGroupBranch() argument
632 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
635 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
645 const MCDisassembler *Decoder) { in DecodePOP35GroupBranchMMR6() argument
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
659 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
661 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
666 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
679 const MCDisassembler *Decoder) { in DecodeDaddiGroupBranch() argument
705 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
708 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
718 const MCDisassembler *Decoder) { in DecodePOP37GroupBranchMMR6() argument
725 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
727 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
732 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
734 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
739 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
752 const MCDisassembler *Decoder) { in DecodePOP65GroupBranchMMR6() argument
777 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP65GroupBranchMMR6()
780 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP65GroupBranchMMR6()
791 const MCDisassembler *Decoder) { in DecodePOP75GroupBranchMMR6() argument
816 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP75GroupBranchMMR6()
819 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP75GroupBranchMMR6()
830 const MCDisassembler *Decoder) { in DecodeBlezlGroupBranch() argument
859 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
862 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
873 const MCDisassembler *Decoder) { in DecodeBgtzlGroupBranch() argument
903 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
906 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
917 const MCDisassembler *Decoder) { in DecodeBgtzGroupBranch() argument
951 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
955 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
966 const MCDisassembler *Decoder) { in DecodeBlezGroupBranch() argument
995 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezGroupBranch()
997 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezGroupBranch()
1009 const MCDisassembler *Decoder) { in DecodeDEXT() argument
1038 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); in DecodeDEXT()
1040 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); in DecodeDEXT()
1051 const MCDisassembler *Decoder) { in DecodeDINS() argument
1081 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); in DecodeDINS()
1083 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); in DecodeDINS()
1090 // Auto-generated decoder wouldn't add the third operand for CRC32*.
1093 const MCDisassembler *Decoder) { in DecodeCRC() argument
1096 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeCRC()
1098 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeCRC()
1100 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeCRC()
1177 // Calling the auto-generated decoder function for microMIPS32R6 in getInstruction()
1188 // Calling the auto-generated decoder function for microMIPS 16-bit in getInstruction()
1204 // Calling the auto-generated decoder function. in getInstruction()
1214 // Calling the auto-generated decoder function. in getInstruction()
1328 // Calling the auto-generated decoder function. in getInstruction()
1339 const MCDisassembler *Decoder) { in DecodeCPU16RegsRegisterClass() argument
1345 const MCDisassembler *Decoder) { in DecodeGPR64RegisterClass() argument
1349 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); in DecodeGPR64RegisterClass()
1356 const MCDisassembler *Decoder) { in DecodeGPRMM16RegisterClass() argument
1359 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); in DecodeGPRMM16RegisterClass()
1366 const MCDisassembler *Decoder) { in DecodeGPRMM16ZeroRegisterClass() argument
1369 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); in DecodeGPRMM16ZeroRegisterClass()
1376 const MCDisassembler *Decoder) { in DecodeGPRMM16MovePRegisterClass() argument
1379 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); in DecodeGPRMM16MovePRegisterClass()
1386 const MCDisassembler *Decoder) { in DecodeGPR32RegisterClass() argument
1389 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); in DecodeGPR32RegisterClass()
1396 const MCDisassembler *Decoder) { in DecodePtrRegisterClass() argument
1397 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) in DecodePtrRegisterClass()
1398 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); in DecodePtrRegisterClass()
1400 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); in DecodePtrRegisterClass()
1405 const MCDisassembler *Decoder) { in DecodeDSPRRegisterClass() argument
1406 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); in DecodeDSPRRegisterClass()
1411 const MCDisassembler *Decoder) { in DecodeFGR64RegisterClass() argument
1415 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); in DecodeFGR64RegisterClass()
1422 const MCDisassembler *Decoder) { in DecodeFGR32RegisterClass() argument
1426 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); in DecodeFGR32RegisterClass()
1433 const MCDisassembler *Decoder) { in DecodeCCRRegisterClass() argument
1436 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); in DecodeCCRRegisterClass()
1443 const MCDisassembler *Decoder) { in DecodeFCCRegisterClass() argument
1446 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); in DecodeFCCRegisterClass()
1453 const MCDisassembler *Decoder) { in DecodeFGRCCRegisterClass() argument
1457 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); in DecodeFGRCCRegisterClass()
1463 const MCDisassembler *Decoder) { in DecodeMem() argument
1468 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMem()
1469 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMem()
1483 const MCDisassembler *Decoder) { in DecodeMemEVA() argument
1488 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemEVA()
1489 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemEVA()
1503 const MCDisassembler *Decoder) { in DecodeLoadByte15() argument
1508 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeLoadByte15()
1509 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeLoadByte15()
1519 const MCDisassembler *Decoder) { in DecodeCacheOp() argument
1524 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheOp()
1535 const MCDisassembler *Decoder) { in DecodeCacheOpMM() argument
1540 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheOpMM()
1551 const MCDisassembler *Decoder) { in DecodePrefeOpMM() argument
1556 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodePrefeOpMM()
1567 const MCDisassembler *Decoder) { in DecodeCacheeOp_CacheOpR6() argument
1572 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheeOp_CacheOpR6()
1582 const MCDisassembler *Decoder) { in DecodeSyncI() argument
1586 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSyncI()
1596 const MCDisassembler *Decoder) { in DecodeSyncI_MM() argument
1600 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSyncI_MM()
1609 const MCDisassembler *Decoder) { in DecodeSynciR6() argument
1613 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSynciR6()
1623 const MCDisassembler *Decoder) { in DecodeMSA128Mem() argument
1628 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); in DecodeMSA128Mem()
1629 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMSA128Mem()
1670 const MCDisassembler *Decoder) { in DecodeMemMMImm4() argument
1679 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) in DecodeMemMMImm4()
1689 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) in DecodeMemMMImm4()
1695 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) in DecodeMemMMImm4()
1727 const MCDisassembler *Decoder) { in DecodeMemMMSPImm5Lsl2() argument
1731 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMSPImm5Lsl2()
1742 const MCDisassembler *Decoder) { in DecodeMemMMGPImm7Lsl2() argument
1746 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMGPImm7Lsl2()
1757 const MCDisassembler *Decoder) { in DecodeMemMMReglistImm4Lsl2() argument
1769 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) in DecodeMemMMReglistImm4Lsl2()
1781 const MCDisassembler *Decoder) { in DecodeMemMMImm9() argument
1786 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm9()
1787 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm9()
1801 const MCDisassembler *Decoder) { in DecodeMemMMImm12() argument
1806 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm12()
1807 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm12()
1812 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) in DecodeMemMMImm12()
1835 const MCDisassembler *Decoder) { in DecodeMemMMImm16() argument
1840 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm16()
1841 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm16()
1851 const MCDisassembler *Decoder) { in DecodeFMem() argument
1856 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); in DecodeFMem()
1857 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem()
1868 const MCDisassembler *Decoder) { in DecodeFMemMMR2() argument
1875 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); in DecodeFMemMMR2()
1876 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemMMR2()
1886 const MCDisassembler *Decoder) { in DecodeFMem2() argument
1891 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMem2()
1892 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem2()
1902 const MCDisassembler *Decoder) { in DecodeFMem3() argument
1907 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); in DecodeFMem3()
1908 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem3()
1919 const MCDisassembler *Decoder) { in DecodeFMemCop2R6() argument
1924 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMemCop2R6()
1925 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemCop2R6()
1936 const MCDisassembler *Decoder) { in DecodeFMemCop2MMR6() argument
1941 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMemCop2MMR6()
1942 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemCop2MMR6()
1953 const MCDisassembler *Decoder) { in DecodeSpecial3LlSc() argument
1958 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); in DecodeSpecial3LlSc()
1959 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSpecial3LlSc()
1974 const MCDisassembler *Decoder) { in DecodeHWRegsRegisterClass() argument
1984 const MCDisassembler *Decoder) { in DecodeAFGR64RegisterClass() argument
1988 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); in DecodeAFGR64RegisterClass()
1995 const MCDisassembler *Decoder) { in DecodeACC64DSPRegisterClass() argument
1999 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); in DecodeACC64DSPRegisterClass()
2006 const MCDisassembler *Decoder) { in DecodeHI32DSPRegisterClass() argument
2010 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); in DecodeHI32DSPRegisterClass()
2017 const MCDisassembler *Decoder) { in DecodeLO32DSPRegisterClass() argument
2021 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); in DecodeLO32DSPRegisterClass()
2028 const MCDisassembler *Decoder) { in DecodeMSA128BRegisterClass() argument
2032 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); in DecodeMSA128BRegisterClass()
2039 const MCDisassembler *Decoder) { in DecodeMSA128HRegisterClass() argument
2043 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); in DecodeMSA128HRegisterClass()
2050 const MCDisassembler *Decoder) { in DecodeMSA128WRegisterClass() argument
2054 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); in DecodeMSA128WRegisterClass()
2061 const MCDisassembler *Decoder) { in DecodeMSA128DRegisterClass() argument
2065 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); in DecodeMSA128DRegisterClass()
2072 const MCDisassembler *Decoder) { in DecodeMSACtrlRegisterClass() argument
2076 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); in DecodeMSACtrlRegisterClass()
2083 const MCDisassembler *Decoder) { in DecodeCOP0RegisterClass() argument
2087 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); in DecodeCOP0RegisterClass()
2094 const MCDisassembler *Decoder) { in DecodeCOP2RegisterClass() argument
2098 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); in DecodeCOP2RegisterClass()
2105 const MCDisassembler *Decoder) { in DecodeBranchTarget() argument
2113 const MCDisassembler *Decoder) { in DecodeBranchTarget1SImm16() argument
2121 const MCDisassembler *Decoder) { in DecodeJumpTarget() argument
2129 const MCDisassembler *Decoder) { in DecodeBranchTarget21() argument
2138 const MCDisassembler *Decoder) { in DecodeBranchTarget21MM() argument
2147 const MCDisassembler *Decoder) { in DecodeBranchTarget26() argument
2156 const MCDisassembler *Decoder) { in DecodeBranchTarget7MM() argument
2164 const MCDisassembler *Decoder) { in DecodeBranchTarget10MM() argument
2172 const MCDisassembler *Decoder) { in DecodeBranchTargetMM() argument
2180 const MCDisassembler *Decoder) { in DecodeBranchTarget26MM() argument
2189 const MCDisassembler *Decoder) { in DecodeJumpTargetMM() argument
2197 const MCDisassembler *Decoder) { in DecodeJumpTargetXMM() argument
2205 const MCDisassembler *Decoder) { in DecodeAddiur2Simm7() argument
2217 const MCDisassembler *Decoder) { in DecodeLi16Imm() argument
2227 const MCDisassembler *Decoder) { in DecodePOOL16BEncodedField() argument
2235 const MCDisassembler *Decoder) { in DecodeUImmWithOffsetAndScale() argument
2245 const MCDisassembler *Decoder) { in DecodeSImmWithOffsetAndScale() argument
2252 const MCDisassembler *Decoder) { in DecodeInsSize() argument
2264 const MCDisassembler *Decoder) { in DecodeSimm19Lsl2() argument
2271 const MCDisassembler *Decoder) { in DecodeSimm18Lsl3() argument
2277 const MCDisassembler *Decoder) { in DecodeSimm9SP() argument
2292 const MCDisassembler *Decoder) { in DecodeANDI16Imm() argument
2303 const MCDisassembler *Decoder) { in DecodeRegListOperand() argument
2331 const MCDisassembler *Decoder) { in DecodeRegListOperand16() argument
2355 const MCDisassembler *Decoder) { in DecodeMovePOperands() argument
2357 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == in DecodeMovePOperands()
2362 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) in DecodeMovePOperands()
2367 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == in DecodeMovePOperands()
2372 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == in DecodeMovePOperands()
2381 const MCDisassembler *Decoder) { in DecodeMovePRegPair() argument
2424 const MCDisassembler *Decoder) { in DecodeSimm23Lsl2() argument
2432 const MCDisassembler *Decoder) { in DecodeBgtzGroupBranchMMR6() argument
2467 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); in DecodeBgtzGroupBranchMMR6()
2471 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); in DecodeBgtzGroupBranchMMR6()
2481 const MCDisassembler *Decoder) { in DecodeBlezGroupBranchMMR6() argument
2512 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); in DecodeBlezGroupBranchMMR6()
2514 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); in DecodeBlezGroupBranchMMR6()
2521 // This instruction does not have a working decoder, and needs to be
2526 const MCDisassembler *Decoder) { in DecodeFIXMEInstruction() argument