Lines Matching full:src1
15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
22 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
25 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
28 def : Pat <(v64i1 (bitconvert (v16i32 HvxVR:$src1))),
29 (v64i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
31 def : Pat <(v64i1 (bitconvert (v32i16 HvxVR:$src1))),
32 (v64i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
34 def : Pat <(v64i1 (bitconvert (v64i8 HvxVR:$src1))),
35 (v64i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
37 def : Pat <(v16i32 (bitconvert (v64i1 HvxQR:$src1))),
38 (v16i32 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
40 def : Pat <(v32i16 (bitconvert (v64i1 HvxQR:$src1))),
41 (v32i16 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
43 def : Pat <(v64i8 (bitconvert (v64i1 HvxQR:$src1))),
44 (v64i8 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
46 def : Pat <(v128i1 (bitconvert (v32i32 HvxVR:$src1))),
47 (v128i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
49 def : Pat <(v128i1 (bitconvert (v64i16 HvxVR:$src1))),
50 (v128i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
52 def : Pat <(v128i1 (bitconvert (v128i8 HvxVR:$src1))),
53 (v128i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
55 def : Pat <(v32i32 (bitconvert (v128i1 HvxQR:$src1))),
56 (v32i32 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
58 def : Pat <(v64i16 (bitconvert (v128i1 HvxQR:$src1))),
59 (v64i16 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
61 def : Pat <(v128i8 (bitconvert (v128i1 HvxQR:$src1))),
62 (v128i8 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
65 def : Pat <(store (v64i1 HvxQR:$src1), (i32 IntRegs:$addr)),
67 (v16i32 (V6_vandqrt (v64i1 HvxQR:$src1),
74 def : Pat <(store (v128i1 HvxQR:$src1), (i32 IntRegs:$addr)),
76 (v32i32 (V6_vandqrt (v128i1 HvxQR:$src1),
85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
86 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
87 (MI IntRegs:$src1)>;
91 def: Pat<(IntID HvxVR:$src1),
92 (MI HvxVR:$src1)>;
94 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1),
95 (MI HvxVR:$src1)>;
99 def: Pat<(IntID HvxWR:$src1),
100 (MI HvxWR:$src1)>;
102 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1),
103 (MI HvxWR:$src1)>;
107 def: Pat<(IntID HvxQR:$src1),
108 (MI HvxQR:$src1)>;
110 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1),
111 (MI HvxQR:$src1)>;
115 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
116 (MI HvxWR:$src1, IntRegs:$src2)>;
118 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2),
119 (MI HvxWR:$src1, IntRegs:$src2)>;
123 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
124 (MI HvxVR:$src1, IntRegs:$src2)>;
126 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2),
127 (MI HvxVR:$src1, IntRegs:$src2)>;
131 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
132 (MI HvxWR:$src1, HvxVR:$src2)>;
134 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2),
135 (MI HvxWR:$src1, HvxVR:$src2)>;
139 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
140 (MI HvxWR:$src1, HvxWR:$src2)>;
142 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
143 (MI HvxWR:$src1, HvxWR:$src2)>;
147 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
148 (MI HvxVR:$src1, HvxVR:$src2)>;
150 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
151 (MI HvxVR:$src1, HvxVR:$src2)>;
155 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
156 (MI HvxQR:$src1, IntRegs:$src2)>;
158 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
159 (MI HvxQR:$src1, IntRegs:$src2)>;
163 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
164 (MI HvxQR:$src1, HvxQR:$src2)>;
166 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
167 (MI HvxQR:$src1, HvxQR:$src2)>;
171 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
172 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
174 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
176 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
180 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
181 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
183 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
185 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
189 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
190 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
192 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
194 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
198 def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3),
199 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
201 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxWR:$src2,
203 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>;
207 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3),
208 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
210 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
212 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>;
216 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
217 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
219 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
221 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
225 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3),
226 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
228 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
230 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>;
234 def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
235 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
237 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
239 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>;
244 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3),
245 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
247 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2,
249 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>;
253 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
254 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
256 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1,
258 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>;
262 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3),
263 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
265 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1,
267 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>;
271 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4),
272 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
274 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
276 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>;
280 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
281 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
283 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
285 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
289 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4),
290 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;
292 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
294 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>;