Lines Matching full:hexagon
28 #define DEBUG_TYPE "hexagon-cext-opt"
33 "hexagon-cext-threshold", cl::init(3), cl::Hidden,
37 ReplaceLimit("hexagon-cext-limit", cl::init(0), cl::Hidden,
227 return "Hexagon constant-extender optimization"; in getPassName()
570 INITIALIZE_PASS_BEGIN(HexagonConstExtenders, "hexagon-cext-opt",
571 "Hexagon constant-extender optimization", false, false)
573 INITIALIZE_PASS_END(HexagonConstExtenders, "hexagon-cext-opt",
574 "Hexagon constant-extender optimization", false, false)
801 case Hexagon::S4_storeirbt_io: in isStoreImmediate()
802 case Hexagon::S4_storeirbf_io: in isStoreImmediate()
803 case Hexagon::S4_storeirht_io: in isStoreImmediate()
804 case Hexagon::S4_storeirhf_io: in isStoreImmediate()
805 case Hexagon::S4_storeirit_io: in isStoreImmediate()
806 case Hexagon::S4_storeirif_io: in isStoreImmediate()
807 case Hexagon::S4_storeirb_io: in isStoreImmediate()
808 case Hexagon::S4_storeirh_io: in isStoreImmediate()
809 case Hexagon::S4_storeiri_io: in isStoreImmediate()
819 case Hexagon::L2_loadrub_io: in isRegOffOpcode()
820 case Hexagon::L2_loadrb_io: in isRegOffOpcode()
821 case Hexagon::L2_loadruh_io: in isRegOffOpcode()
822 case Hexagon::L2_loadrh_io: in isRegOffOpcode()
823 case Hexagon::L2_loadri_io: in isRegOffOpcode()
824 case Hexagon::L2_loadrd_io: in isRegOffOpcode()
825 case Hexagon::L2_loadbzw2_io: in isRegOffOpcode()
826 case Hexagon::L2_loadbzw4_io: in isRegOffOpcode()
827 case Hexagon::L2_loadbsw2_io: in isRegOffOpcode()
828 case Hexagon::L2_loadbsw4_io: in isRegOffOpcode()
829 case Hexagon::L2_loadalignh_io: in isRegOffOpcode()
830 case Hexagon::L2_loadalignb_io: in isRegOffOpcode()
831 case Hexagon::L2_ploadrubt_io: in isRegOffOpcode()
832 case Hexagon::L2_ploadrubf_io: in isRegOffOpcode()
833 case Hexagon::L2_ploadrbt_io: in isRegOffOpcode()
834 case Hexagon::L2_ploadrbf_io: in isRegOffOpcode()
835 case Hexagon::L2_ploadruht_io: in isRegOffOpcode()
836 case Hexagon::L2_ploadruhf_io: in isRegOffOpcode()
837 case Hexagon::L2_ploadrht_io: in isRegOffOpcode()
838 case Hexagon::L2_ploadrhf_io: in isRegOffOpcode()
839 case Hexagon::L2_ploadrit_io: in isRegOffOpcode()
840 case Hexagon::L2_ploadrif_io: in isRegOffOpcode()
841 case Hexagon::L2_ploadrdt_io: in isRegOffOpcode()
842 case Hexagon::L2_ploadrdf_io: in isRegOffOpcode()
843 case Hexagon::S2_storerb_io: in isRegOffOpcode()
844 case Hexagon::S2_storerh_io: in isRegOffOpcode()
845 case Hexagon::S2_storerf_io: in isRegOffOpcode()
846 case Hexagon::S2_storeri_io: in isRegOffOpcode()
847 case Hexagon::S2_storerd_io: in isRegOffOpcode()
848 case Hexagon::S2_pstorerbt_io: in isRegOffOpcode()
849 case Hexagon::S2_pstorerbf_io: in isRegOffOpcode()
850 case Hexagon::S2_pstorerht_io: in isRegOffOpcode()
851 case Hexagon::S2_pstorerhf_io: in isRegOffOpcode()
852 case Hexagon::S2_pstorerft_io: in isRegOffOpcode()
853 case Hexagon::S2_pstorerff_io: in isRegOffOpcode()
854 case Hexagon::S2_pstorerit_io: in isRegOffOpcode()
855 case Hexagon::S2_pstorerif_io: in isRegOffOpcode()
856 case Hexagon::S2_pstorerdt_io: in isRegOffOpcode()
857 case Hexagon::S2_pstorerdf_io: in isRegOffOpcode()
858 case Hexagon::A2_addi: in isRegOffOpcode()
869 using namespace Hexagon; in getRegOffOpcode()
968 case Hexagon::A2_addi: return Hexagon::A2_add; in getDirectRegReplacement()
969 case Hexagon::A2_andir: return Hexagon::A2_and; in getDirectRegReplacement()
970 case Hexagon::A2_combineii: return Hexagon::A4_combineri; in getDirectRegReplacement()
971 case Hexagon::A2_orir: return Hexagon::A2_or; in getDirectRegReplacement()
972 case Hexagon::A2_paddif: return Hexagon::A2_paddf; in getDirectRegReplacement()
973 case Hexagon::A2_paddit: return Hexagon::A2_paddt; in getDirectRegReplacement()
974 case Hexagon::A2_subri: return Hexagon::A2_sub; in getDirectRegReplacement()
975 case Hexagon::A2_tfrsi: return TargetOpcode::COPY; in getDirectRegReplacement()
976 case Hexagon::A4_cmpbeqi: return Hexagon::A4_cmpbeq; in getDirectRegReplacement()
977 case Hexagon::A4_cmpbgti: return Hexagon::A4_cmpbgt; in getDirectRegReplacement()
978 case Hexagon::A4_cmpbgtui: return Hexagon::A4_cmpbgtu; in getDirectRegReplacement()
979 case Hexagon::A4_cmpheqi: return Hexagon::A4_cmpheq; in getDirectRegReplacement()
980 case Hexagon::A4_cmphgti: return Hexagon::A4_cmphgt; in getDirectRegReplacement()
981 case Hexagon::A4_cmphgtui: return Hexagon::A4_cmphgtu; in getDirectRegReplacement()
982 case Hexagon::A4_combineii: return Hexagon::A4_combineir; in getDirectRegReplacement()
983 case Hexagon::A4_combineir: return TargetOpcode::REG_SEQUENCE; in getDirectRegReplacement()
984 case Hexagon::A4_combineri: return TargetOpcode::REG_SEQUENCE; in getDirectRegReplacement()
985 case Hexagon::A4_rcmpeqi: return Hexagon::A4_rcmpeq; in getDirectRegReplacement()
986 case Hexagon::A4_rcmpneqi: return Hexagon::A4_rcmpneq; in getDirectRegReplacement()
987 case Hexagon::C2_cmoveif: return Hexagon::A2_tfrpf; in getDirectRegReplacement()
988 case Hexagon::C2_cmoveit: return Hexagon::A2_tfrpt; in getDirectRegReplacement()
989 case Hexagon::C2_cmpeqi: return Hexagon::C2_cmpeq; in getDirectRegReplacement()
990 case Hexagon::C2_cmpgti: return Hexagon::C2_cmpgt; in getDirectRegReplacement()
991 case Hexagon::C2_cmpgtui: return Hexagon::C2_cmpgtu; in getDirectRegReplacement()
992 case Hexagon::C2_muxii: return Hexagon::C2_muxir; in getDirectRegReplacement()
993 case Hexagon::C2_muxir: return Hexagon::C2_mux; in getDirectRegReplacement()
994 case Hexagon::C2_muxri: return Hexagon::C2_mux; in getDirectRegReplacement()
995 case Hexagon::C4_cmpltei: return Hexagon::C4_cmplte; in getDirectRegReplacement()
996 case Hexagon::C4_cmplteui: return Hexagon::C4_cmplteu; in getDirectRegReplacement()
997 case Hexagon::C4_cmpneqi: return Hexagon::C4_cmpneq; in getDirectRegReplacement()
998 case Hexagon::M2_accii: return Hexagon::M2_acci; // T -> T in getDirectRegReplacement()
1000 case Hexagon::M2_macsip: return Hexagon::M2_maci; // T -> T in getDirectRegReplacement()
1001 case Hexagon::M2_mpysin: return Hexagon::M2_mpyi; in getDirectRegReplacement()
1002 case Hexagon::M2_mpysip: return Hexagon::M2_mpyi; in getDirectRegReplacement()
1003 case Hexagon::M2_mpysmi: return Hexagon::M2_mpyi; in getDirectRegReplacement()
1004 case Hexagon::M2_naccii: return Hexagon::M2_nacci; // T -> T in getDirectRegReplacement()
1005 case Hexagon::M4_mpyri_addi: return Hexagon::M4_mpyri_addr; in getDirectRegReplacement()
1006 case Hexagon::M4_mpyri_addr: return Hexagon::M4_mpyrr_addr; // _ -> T in getDirectRegReplacement()
1007 case Hexagon::M4_mpyrr_addi: return Hexagon::M4_mpyrr_addr; // _ -> T in getDirectRegReplacement()
1008 case Hexagon::S4_addaddi: return Hexagon::M2_acci; // _ -> T in getDirectRegReplacement()
1009 case Hexagon::S4_addi_asl_ri: return Hexagon::S2_asl_i_r_acc; // T -> T in getDirectRegReplacement()
1010 case Hexagon::S4_addi_lsr_ri: return Hexagon::S2_lsr_i_r_acc; // T -> T in getDirectRegReplacement()
1011 case Hexagon::S4_andi_asl_ri: return Hexagon::S2_asl_i_r_and; // T -> T in getDirectRegReplacement()
1012 case Hexagon::S4_andi_lsr_ri: return Hexagon::S2_lsr_i_r_and; // T -> T in getDirectRegReplacement()
1013 case Hexagon::S4_ori_asl_ri: return Hexagon::S2_asl_i_r_or; // T -> T in getDirectRegReplacement()
1014 case Hexagon::S4_ori_lsr_ri: return Hexagon::S2_lsr_i_r_or; // T -> T in getDirectRegReplacement()
1015 case Hexagon::S4_subaddi: return Hexagon::M2_subacc; // _ -> T in getDirectRegReplacement()
1016 case Hexagon::S4_subi_asl_ri: return Hexagon::S2_asl_i_r_nac; // T -> T in getDirectRegReplacement()
1017 case Hexagon::S4_subi_lsr_ri: return Hexagon::S2_lsr_i_r_nac; // T -> T in getDirectRegReplacement()
1020 case Hexagon::S4_storeirbf_io: return Hexagon::S2_pstorerbf_io; in getDirectRegReplacement()
1021 case Hexagon::S4_storeirb_io: return Hexagon::S2_storerb_io; in getDirectRegReplacement()
1022 case Hexagon::S4_storeirbt_io: return Hexagon::S2_pstorerbt_io; in getDirectRegReplacement()
1023 case Hexagon::S4_storeirhf_io: return Hexagon::S2_pstorerhf_io; in getDirectRegReplacement()
1024 case Hexagon::S4_storeirh_io: return Hexagon::S2_storerh_io; in getDirectRegReplacement()
1025 case Hexagon::S4_storeirht_io: return Hexagon::S2_pstorerht_io; in getDirectRegReplacement()
1026 case Hexagon::S4_storeirif_io: return Hexagon::S2_pstorerif_io; in getDirectRegReplacement()
1027 case Hexagon::S4_storeiri_io: return Hexagon::S2_storeri_io; in getDirectRegReplacement()
1028 case Hexagon::S4_storeirit_io: return Hexagon::S2_pstorerit_io; in getDirectRegReplacement()
1056 if (Opc == Hexagon::A2_addi) { in getOffsetRange()
1108 case Hexagon::A2_addi: // s16 in getOffsetRange()
1110 case Hexagon::A2_subri: // s10 in getOffsetRange()
1183 case Hexagon::A2_tfrsi: // (Rd: ## + __<<_) in recordExtender()
1187 case Hexagon::A2_combineii: // (Rd: ## + __<<_) in recordExtender()
1188 case Hexagon::A4_combineir: in recordExtender()
1189 ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_hi }; in recordExtender()
1192 case Hexagon::A4_combineri: // (Rd: ## + __<<_) in recordExtender()
1193 ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_lo }; in recordExtender()
1196 case Hexagon::A2_addi: // (Rd: ## + Rs<<0) in recordExtender()
1200 case Hexagon::M2_accii: // (__: ## + Rs<<0) in recordExtender()
1201 case Hexagon::M2_naccii: in recordExtender()
1202 case Hexagon::S4_addaddi: in recordExtender()
1205 case Hexagon::A2_subri: // (Rd: ## - Rs<<0) in recordExtender()
1210 case Hexagon::S4_subaddi: // (__: ## - Rs<<0) in recordExtender()
1240 case Hexagon::M2_macsin: // There is no Rx -= mpyi(Rs,Rt). in collectInstr()
1241 case Hexagon::C4_addipc: in collectInstr()
1242 case Hexagon::S4_or_andi: in collectInstr()
1243 case Hexagon::S4_or_andix: in collectInstr()
1244 case Hexagon::S4_or_ori: in collectInstr()
1290 if (ED.UseMI->getOpcode() == Hexagon::A2_tfrsi) { in assignInits()
1533 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in insertInitializer()
1547 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR) in insertInitializer()
1554 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR) in insertInitializer()
1559 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1564 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1570 unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri in insertInitializer()
1571 : Hexagon::S4_addi_asl_ri; in insertInitializer()
1581 llvm::Register TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in insertInitializer()
1582 BuildMI(MBB, At, dl, HII->get(Hexagon::S2_asl_i_r), TmpR) in insertInitializer()
1586 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1590 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1619 if (ExtOpc == Hexagon::A4_combineri) in replaceInstrExact()
1623 .addImm(Hexagon::isub_hi) in replaceInstrExact()
1625 .addImm(Hexagon::isub_lo); in replaceInstrExact()
1626 else if (ExtOpc == Hexagon::A4_combineir) in replaceInstrExact()
1630 .addImm(Hexagon::isub_hi) in replaceInstrExact()
1632 .addImm(Hexagon::isub_lo); in replaceInstrExact()
1638 if (ExtOpc == Hexagon::C2_cmpgei || ExtOpc == Hexagon::C2_cmpgeui) { in replaceInstrExact()
1639 unsigned NewOpc = ExtOpc == Hexagon::C2_cmpgei ? Hexagon::C2_cmplt in replaceInstrExact()
1640 : Hexagon::C2_cmpltu; in replaceInstrExact()
1731 if (ExtOpc == Hexagon::A2_tfrsi) { in replaceInstrExpr()
1741 assert(IdxOpc == Hexagon::A2_addi); in replaceInstrExpr()
1776 if (ExtOpc == Hexagon::A2_addi || ExtOpc == Hexagon::A2_subri) { in replaceInstrExpr()
1781 bool IsAddi = ExtOpc == Hexagon::A2_addi; in replaceInstrExpr()
1794 if (ExtOpc == Hexagon::M2_accii || ExtOpc == Hexagon::M2_naccii || in replaceInstrExpr()
1795 ExtOpc == Hexagon::S4_addaddi || ExtOpc == Hexagon::S4_subaddi) { in replaceInstrExpr()
1804 bool IsSub = ExtOpc == Hexagon::S4_subaddi; in replaceInstrExpr()
1809 unsigned NewOpc = ExtOpc == Hexagon::M2_naccii ? Hexagon::A2_sub in replaceInstrExpr()
1810 : Hexagon::A2_add; in replaceInstrExpr()
1949 MRI->getRegClass(Op.getReg()) != &Hexagon::PredRegsRegClass) in getPredicateOp()